• Journal of information and communication convergence engineering
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• v.18 no.4
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• pp.222-229
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• 2020

Recent multi-core processors for smart devices use per-core dynamic voltage and frequency scaling (DVFS) that enables independent voltage and frequency control of cores. However, because the conventional task scheduler was originally designed for per-core DVFS disabled processors, it cannot effectively utilize the per-core DVFS and simply allocates tasks evenly across all cores to core utilization with the same CPU frequency. Hence, we propose a novel task scheduler to effectively utilize percore DVFS, which enables each core to have the appropriate frequency, thereby improving performance and decreasing energy consumption. The proposed scheduler classifies applications into two types, based on performance-sensitivity and allows a performance-sensitive application to have a dedicated core, which maximizes core utilization. The experimental evaluations with a real off-the-shelf smart device showed that the proposed task scheduler reduced 13.6% of CPU energy (up to 28.3%) and 3.4% of execution time (up to 24.5%) on average, as compared to the conventional task scheduler.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.4 no.2
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• pp.37-43
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• 2005

A simple scheduler satisfying the proportional fairness (PF) was introduced in wireless access networks and revealed that it can achieve a good compromise between total throughput and user fairness. Though it has received much attention for some time, its application was mainly restricted to the single channel systems. In this paper, we study how to implement the PF scheduler in the multi-channel environments such as OFDMA/TDMA. Besides the traditional PF-SC scheme, we propose a new PF-OPT scheme that is the genuine PF scheduler in a sense of maximizing the total log-utility of users. The simulation results show that PF-OPT gives large throughput under the heterogeneous subchannel statistics.

• Proceedings of the Korea Contents Association Conference
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• 2006.11a
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• pp.3-6
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• 2006

The Web2.0(Next Generation Web Service) is receiving attention by computer industry. Therefore Ajax(Asynchonous Javascript And in), a key RIA(Rich Internet Application) technology of Web 2.0 applications, has also been a matter of interest. And multiple Web applications which are based on Ajax are being developed and delivered. This paper deals with 'Scheduler Applications/Services' of the web application that utilize Ajax. Plus, this paper is aimed at developing, Project Management Scheduler and Project Roadmap, using web applications that utilize Ajax.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.5
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• pp.236-239
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• 2006

A wireless MAC scheduler that provides a high level of quality-of-service (QoS) for video-on-demand (VOD) applications while achieving a reasonable level of system throughput is proposed. The proposed scheduler considers both channel qualities of mobiles and the urgency of real-time packets coming from VOD applications in a cross-layer approach between application and MAC layers.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.4
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• pp.193-199
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• 2012

Virtualization allows multiple commodity operating systems to share on a single physical machine. Resource allocation among virtual machines is a key to determine virtual machine performance. To satisfy time-sensitive task on a domain, hypervisor needs to observe the resource requirements and allocates proper amount of CPU resources in a timely manner. In this paper, we propose a realtime credit scheduler for latency sensitive application on virtual machines. The key idea is to register a time event in the Xen hypervisor. Experiment result shows that the proposed scheme is superior to Credit scheduler.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.1
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• pp.38-46
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• 2011

The OPRoS (Open Platform for Robotic Service) framework provides uniform operating environment for service robots. As an OPRoS-based service robot has to support real-time as well as non-real-time applications, application of Windows NT kernel based operating system can be restrictive. On the other hand, various benefits such as rich library and device support and abundant developer pool can be enjoyed when service robots are built on Windows NT. The paper presents a user-mode component scheduler of OPRoS, which can provide near real-time scheduling service on Windows NT based on the restricted real-time features of Windows NT kernel. The component scheduler thread with the highest real-time priority in Windows NT system acquires CPU control. And then the component scheduler suspends and resumes each periodic component executors based on its priority and precedence dependency so that the component executors are scheduled in the preemptive manner. We show experiment analysis on the performance limitations of the proposed scheduling technique. The analysis and experimental results show that the proposed scheduler guarantees highly reliable timing down to the resolution of 10ms.

• The KIPS Transactions:PartA
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• v.12A no.5 s.95
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• pp.375-384
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• 2005

General purpose operating systems are Increasingly being used for serving time-sensitive applications. These applications require soft real-time characteristics from the kernel and from other system-level services. In this paper, we explore various operating systems techniques needed to support time-sensitive applications and describe the design of MUSMA(Multi-level Scheduler for Multimedia Application). MUSMA is a framework that combination of user-level top scheduler and kernel-level bottom scheduler. We develope MUSMA in linux environment and it's performance is evaluated. Experiment result shows that it is possible to satisfy the constraints of multimedia in a general purpose operating system without significantly compromising the performance of non-realtime applications.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.7
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• pp.788-812
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• 1999

본 논문에서는 범용 워크스테이션 환경하에서 수행되는 멀티미디어 응용프로그램(application)을 지원하기 위한 비례지분 방식의 CPU 스케줄러를 제시한다. 이러한 목적을 위하여 일반적 태스크의 지원을 위해 설계된 스트라이드 스케줄러를 확장한다. 멀티미디어 응용프로그램의 시간 요구사항을 명시하기 위하여 새로운 스케줄링 파라미터들을 도입한다. 비율조정기를 도입한 결과 스케줄링의 정확도의 오차는 O(1)로 감소하였다. 별도의 태스크 그룹을 설정하여 상대적 지분과 절대적 지분을 부여했다. 모의실험을 사용하여 스케줄러의 성능을 평가하였다. 그 결과, 제안된 스케줄러는 증가된 정확도와 적응성 및 유연성을 가짐을 알 수 있었다. Abstract This paper presents a proportional-share CPU scheduler which can support multimedia applications in a general-purpose workstation environment. For this purpose, we have extended the stride scheduler which is designed originally for conventional tasks. New scheduling parameters are introduced to specify timing requirements of multimedia applications. Through the use of the rate regulator, the accuracy error of the scheduling is reduced to O(1). Separate task groups are proposed to represent both relative shares and absolute shares. The proposed scheduler is evaluated using a simulation study. The results show that the proposed scheduler achieves improved accuracy and adaptability as well as flexibility.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10b
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• pp.1817-1822
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• 1991

A method of reducing overhead caused by the processor synchronization process and common memory accesses in finely grained tasks is described. We propose a scheduler which considers the preparation time during searching to minimize the redundant accesses to shared memory. Since the suggested hardware (synchronizer) determines the access order of processors and bus arbitration simultaneously by including the synchronization process into the bus arbitration process, the synchronization time vanishes. Therefore this synchronizer has no overhead caused by the processor synchronization[l]. The proposed scheduler algorithm is processed in parallel. The processes share the upper bound derived by each searching and the lower bound function is built considering the preparation time in order to eliminate as many searches as possible. An application of the proposed method to a multi-DSP system to calculate inverse dynamics for robot arms, showed that the sampling time can be twice shorter than that of the conventional one.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.1 s.232
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• pp.96-106
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• 2005

An integrated single-wafer processing tool, composed of multiple single wafer processing modules, transfer robots, and load locks, has complex routing sequences, and often has critical post-processing residency constraints. Scheduling of these tools is an intricate problem, and testing schedulers with actual tools requires too much time and cost. The Single Wafer Processor (SWP) simulator presented in this paper is to validate an on-line scheduler, and evaluate performance of integrated single-wafer processing tools before the scheduler is actually deployed into real systems. The data transfer between the scheduler and the simulator is carried out with TCP/IP communication using messages and files. The developed simulator consists of six modules, i.e., GUI (Graphic User Interface), emulators, execution system, module managers, analyzer, and 3D animator. The overall framework is built using Microsoft Visual C++, and the animator is embodied using OpenGL API (Application Programming Interface).