• 한국방사선학회논문지
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• 제10권5호
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• pp.299-305
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• 2016

의료장비와 기술의 발달에도 불구하고 췌장암만 유일하게 기타 암질환과 비교하면 오진률이 높고 생존률이 낮은 질환이다. 따라서 췌장암은 조기 발견만이 생존율을 높일 수 있는 유일한 방법이며 췌장암의 정확한 위치를 찾는 것이 중요하다. Dual Point PET/CT 검사를 이용해서 췌장암의 조기 발견을 위한 최적의 Scan method를 제안하였다. PET/CT 검사의 Supine position에서 놓칠 수 있는 해부학적 영역을 환자의 position을 $0^{\circ}$, $30^{\circ}$, $45^{\circ}$, $60^{\circ}$ $75^{\circ}$ 변화에 따른 영상의 특징 및 유효성을 분석하였다. 그 결과 $90^{\circ}$ lateral recumbent position Scan에서 Pancreas tail 판별의 유용성을 발견하였다. Dual Point PET/CT 검사에서 상복부 특히 해부학적 구조상 췌장처럼 인접 장기와 중첩이 있는 경우, 췌장암이 의심될 때 PET/CT 지연검사에서 환자에게 충분한 수분섭취를 한 후 환자의 Position을 테이블과 수직 상태로 돌려 Lt 또는 Rt lateral Recumbent position 상태에서 PET/CT Scan을 시행하므로 위장, 간, 담낭 십이지장, 췌장 등의 장기를 이격시켜 해부학적 판별에 이점을 주는 검사방법 (JJ-Projection: lateral recumbent position scan)을 개발하였다. ROC curve 분석에서 JJ-Projection방법이 기존의 Supine scan 방식에서 얻은 영상보다 민감도가 95.2% 나타났다. 이것은 기존의 검사방식과 비교해볼 때 4.6 % 증가 하였다. 특이도는 87.5%로 6.9% 증가하였다. 조직검사로 생물학적 암으로 확정된 결과치와 비교해 볼 때 정확도는 94.1%로 기존 방식 86%에 비해 8.41 % 증가하였다. 그러므로 Dual Time Point PET/CT를 이용한 췌장암 판별 검사를 할 때 Delay scan에서 lateral recumbent position로 변경해서 Scan 하는 것이 기존의 일반적인 방법인 Supine position Scan보다 췌장암 조기 판별에 유용한 정보를 줄 수 있을 것으로 사료된다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.87-88
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• 2006

In this paper, we propose a new selective scanning scheme based on hand-off path information, which can provide an efficient reducing of delay time. This scheme eliminates almost of the scanning delay time by using Selective Scan based on Experience Path Table(SSEPT) algorithm and also completed hand-off within few milliseconds by using the next candidate channel indexing mechanism. Our scheme reduces the total number of scanning channels as well as the delay time on each channel. From the simulation result, we show that the proposed scheme is advantageous over the legacy schemes in terms of the scanning channels and the total delay time.

• Journal of electromagnetic engineering and science
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• 제14권2호
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• pp.79-81
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• 2014

In B-scan data measured by a pulse-type monostatic borehole radar, target signatures are seriously obscured by two clutters that differ in orientation and intensity. The primary clutter appears as a nearly constant time delay, which is caused by internal ringing between antenna and transceiver in the radar system. The secondary clutter occurs as an oblique time delay due to the guided borehole wave along the logging cable of the radar antenna. This issue led us to perform adaptive filtering processing for orientation-based clutter removal. This letter describes adaptive filtering processing consisting of a combination of edge detection, data rotation, and eigenimage filtering. We show that the hyperbolic signatures of a dormant air-filled tunnel target can be more distinctly enhanced by applying the proposed approach to the B-scan data, which are measured in a well-suited test site for underground tunnel detection.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권8호
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• pp.407-414
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• 2004

In this paper, a new gray scale expression method that divides the scan lines into multiple blocks is suggested. The proposed method can drive 16 sub-fields per 1 TV field in the panel with XGA ($1366{\times}768$) resolution. The on and off states of even subfields depend on the condition of odd subfields. The write address mode is used in the odd subfields, while the erase address mode is used in the even subfields. Because the ramp reset pulse is applied every 2 sub-fields, both the contrast ratio and the dynamic voltage margin are sufficiently obtained in comparison with previous AWD (Address While Display) methods. In realizing 16 subfields, shortening the scan time in the erase address period was important. The X bias voltage in the erase address period affected the minimum address voltage but did not the delay time of the address discharge. The delay time of the address discharge was affected by the address voltage and the time interval between the last sustain discharge and the scanning time. We also evaluated the dynamic false contour. New method shows an improved image quality in horizontal moving, but discontinuous lines were observed at the boundaries of each block in vertical moving

• 한국전기전자재료학회논문지
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• 제18권3호
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• pp.206-211
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• 2005

The device makers want to make higher density chips on the wafer through scale-down. The change of WSix/poly-Si gate film thickness is one of the key issues under 100 nm device structure. As a new device etching process is applied, end point detection(EPD) time delay was occurred in DPS+ poly chamber of Applied Materials. This is a barrier of device shrink because EPD time delay made physical damage on the surface of gate oxide. To investigate the EPD time delay, the experimental test combined with OES(Optical Emission Spectroscopy) and SEM(Scanning Electron Microscopy) was performed using patterned wafers. As a result, a EPD delay time is reduced by a new chamber seasoning and a new wavelength line through plasma scan. Applying a new wavelength of 252 nm makes it successful to call corrected EPD in WSix/poly-Si stack-down gate etching in the DPS+ poly chamber for the current and next generation devices.

• Journal of electromagnetic engineering and science
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• 제6권2호
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• pp.110-116
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• 2006

A reflective array type surface acoustic wave(SAW) dispersive delay line(DDL) with high time-bandwidth at the V/UHF-band is designed and fabricated for compressive receiver applications. This type of the SAW DDL has the properties of the relative bandwidth of 20 %, the time delay of 49.89 usec, the insertion loss of 38.5 dB and the side lobe rejection of 39 dB. In comparison with a commercial SAW DDL, the insertion loss, amplitude ripple and side lobe rejection are improved by $1.5dB{\pm}0.6dB$ and 4 dB respectively. Using the fabricated SAW DDL, the prototype of the compressive receiver is developed. It is composed of RF converter, fast tunable LO, chirp LO, A/D converter, signal processing unit and control unit. This prototype system shows a fine frequency resolution of below 30 kHz with high scan rate.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.339-340
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• 2007

Gradient system에 spiral waveform 입력을 가하면 Hardware limitation에 의하여 만들어지는 gradient fields에 Transient time delay가 발생한다. 이를 보상하기 위하여, Gradient system을 R-L-C 회로로 모델링하여 재구성에 필요한 k-space trajectory를 보정하여 개선된 image를 획득하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.723-728
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• 1999

In this paper, we designed a Circular Path Built-In Self Test circuit and embedded it into a simple 8-bit microprocessor. Register cells of the microprocessor have been modified into Circular Path register cells and each register cells have been connected to form a scan chain. A BIST controller has been designed for controlling BIST operations and its operation has been verified through simulation. The BIST circuit described in this paper has increased size overhead of the microprocessor by 29.8% and delay time in the longest delay path from clock input to output by 2.9㎱.

• 한국통신학회논문지
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• 제39C권6호
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• pp.482-489
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• 2014

본 논문은 IEEE 802.11 환경에서 새로운 AP를 탐색하기 위한 네트워크 스캐닝의 기존 방식을 802.11k의 Measurement Pilot을 활용하여 개선하는 새로운 알고리즘을 제안한다. 그리고 제안한 알고리즘과 종래의 알고리즘을 시뮬레이션 환경에서 비교하여 분석한다. 일반적인 IEEE 802.11을 사용하는 기기들은 탐색 시간이 짧다는 장점을 갖는 능동 탐색(Active Scan)방식을 활용한다. 하지만 이 방식은 수동 탐색(Passive Scan) 방식에 비해 많은 전력사용을 필요로 한다. 본 논문에서 제안하는 탐색 알고리즘은 IEEE 802.11k에서 활용되는 비컨(Beacon)보다 짧은 주기를 갖는 Measurement Pilot을 활용하여 수동 탐색과 능동 탐색의 장점을 취합하여 전력사용을 줄인다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1959-1960
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• 2008

The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the algorithm that it also suggest algorithm that reduce additional circuits and time delay as matching of pattern about 2-type circuits which are CUT(circuit Under Test) and additional circuits so that the designer can detect the wrong location in CUT: Circuit Under Test.