• Title/Summary/Keyword: Scalar Quatization

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Efficient vector-scalar quantization of line spectrum parirs (LSP) (효율적인 벡터-스칼라 Line spectrum pairs(LSP) 양자화 방법)

  • 이인성;남승현
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.2
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    • pp.333-339
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    • 1996
  • In this paper, an effiicent quatization method of line spectrum pairs(LSP) with cascaded structure of vector quantizer and scalar quantizer is proposed. First, input LSP parameters is vector-quantized using a codebook with a moderate number of entries. In the second stage of quantization, the components of residual vector are individution improve the quantizer by the scalar quantizer. The utilization of ordering property and the inclusion of interframe prediction improve the quantizer performance and remove the stability check routine. The new vector-scalar cascaded quantizer using 27 bits/frame shows a transparent quality that an average specytural distortion is 1 dB and the frame proportion with above 2 dB spectral distion is less than 2%.

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The implementation of the color component 2-D DWT Processor for the JPEG 2000 hard-wired encoder (JPEG 2000 Hard-wired Encoder를 위한 칼라 2-D DWT Processor의 구현)

  • Lee, Sung-Mok;Cho, Sung-Dae;Kang, Bong-Soon
    • Journal of the Institute of Convergence Signal Processing
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    • v.9 no.4
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    • pp.321-328
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    • 2008
  • In this paper, we propose the hardware architecture of two-dimensional discrete wavelet transform (2D DWT) and quantization for using JPEG2000. Color 2-D DWT processor is proposed that is to apply to JPEG 2000 Hard-wired Encoder. JPEG 2000 DWT processor uses the Daubechies' (9,7) bi-orthogonal filter, and we design by minimizing error of the DWT transformer by ${\pm}1$ LSB during compression and decompression. We designed the DWT filters that using by using shift and adder structure instead of multiplier structure which raise the hardware complexity. It is improve the operation speed of filters and reduce the hardware complexity. The proposed system is designed by the hardware description language Verilog-HDL and verified by Synopsys Design Analyzer using TSMC 0.25${\mu}m$ ASIC library.

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