• Title/Summary/Keyword: SMT Solver

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Java Memory Model Simulation using SMT Solver (SMT 해결기를 이용한 자바 메모리 모델 시뮬레이션)

  • Lee, Tae-Hoon;Kwon, Gi-Hwon
    • Journal of KIISE:Computing Practices and Letters
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    • v.15 no.1
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    • pp.62-66
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    • 2009
  • Recently developed compilers perform some optimizations in order to speed up the execution time of source program. These optimizations require the transformation of the sequence of program statements. This transformation does not give any problems in a single-threaded program. However, the transformation gives some significant errors in a multi-threaded program. State-of-the-art model checkers such as Java-Pathfinder do not consider the transformation resulted in the optimization step in a compiler since they just consider a single memory model. In this paper, we describe a new technique which is based on SMT solver. The Java Memory Model Simulator based on SMT Solver can compute all possible output of given multi-thread program within one second which, in contrast, Traditional Java Memory Model Simulator takes one minute.

A Verification of Array Overflow in Java Bytecode using SMT-Solver (SMT-Solver 를 사용한 자바바이트코드의 배열 오버플로우 검증)

  • Lee, Sang-Hyup;Kim, Je-Min;Park, Joon-Seok;Yoo, Weon-Hee
    • Proceedings of the Korea Information Processing Society Conference
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    • 2011.04a
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    • pp.261-264
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    • 2011
  • 자바프로그램 검증은 안전하고 정확한 프로그램을 만들기 위한 필수적인 조건이지만 자바언어로 작성된 프로그램은 바이트코드로 작성되어 있는 클래스 파일로 배포되기 때문에 바이트코드에 대한 검증이 필요하다. 하지만 자바 바이트코드는 가독성이 떨어져 중간언어로 변환을 하고 그 중간코드에서 검증에 필요한 조건들을 작성 해야 한다. 이 논문에서는 새로 정의된 중간언어인 BIRS을 통해 컴파일시 검증이 되지 않는 배열 오버플로우에 대한 정적검증을 설명하고 검증 절차에 필요한 명제의 정의와 검증 시 사용되는 SMT-Solver 인 Z3 의 사용법에 대하여 서술하였다.

Analyzing Vulnerable Software Code Using Dynamic Taint and SMT Solver (동적오염분석과 SMT 해석기를 이용한 소프트웨어 보안 취약점 분석 연구)

  • Kim, Sungho;Park, Yongsu
    • KIISE Transactions on Computing Practices
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    • v.21 no.3
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    • pp.257-262
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    • 2015
  • As software grows more complex, it contains more bugs that are not recognized by developers. Attackers can then use exploitable bugs to penetrate systems or spread malicious code. As a representative method, attackers manipulated documents or multimedia files in order to make the software engage in unanticipated behavior. Recently, this method has gained frequent use in A.P.T. In this paper, an automatic analysis method to find software security bugs was proposed. This approach aimed at finding security bugs in the software which can arise from input data such as documents or multimedia. Through dynamic taint analysis, how input data propagation to vulnerable code occurred was tracked, and relevant instructions in relation to input data were found. Next, the relevant instructions were translated to a formula and vulnerable input data were found via the formula using an SMT solver. Using this approach, 6 vulnerable codes were found, and data were input to crash applications such as HWP and Gomplayer.

Model-Based Automatic Test Data Generation Method Using Custom Parser and SMT Solver (커스텀 파서와 SMT 솔버를 활용한 모델 기반 테스트 데이터 생성 기법)

  • Shin, Ki-Wook;Lim, Dong-Jin
    • KIPS Transactions on Software and Data Engineering
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    • v.6 no.8
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    • pp.385-390
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    • 2017
  • Because of the ever-increasing software complexity, model-based development techniques are becoming an essential technique in software development. However, even if model-based techniques are used, the test case generation for complex software is still a challenge to solve. In this paper, we propose a method to generate automatic test cases based on UML model using custom parser and SMT solver. By proposed technique, a test case can be generated even though the model is described in a platform independent language such as action language, or in a platform dependent language. In addition, a concolic execution technique is applied to efficiently generate test cases in the model. In this paper, we present a case study on the power window switch model of Hyundai Santa Fe through the proposed test case generation technique.

Test Case Generation For Simulink/Stateflow Model Using Yices and Model Information (Yices와 모델 정보를 이용한 Simulink/Stateflow 모델의 테스트 케이스 생성 기법)

  • Park, Han Gon;Chung, Kihyun;Choi, Kyunghee
    • KIPS Transactions on Software and Data Engineering
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    • v.6 no.6
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    • pp.293-302
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    • 2017
  • This paper proposes a method that generates test cases from Simulink/Stateflow(SL/SF) using a SMT (Satisfiability Modulo Theory) solver, Yices and information of SL/SF model. The most difficult problem to generate test cases from SL/SF model is to solve reachability problem. In the propose method, Yices and the tables built with the model information are utilized to solve the reachability problem. The method utilizes the SMT model, that is the SL/SF model transformed in Yices. The tables built from SL/SF are used for backward processing of the proposed method and increases test generation efficiency. A commercial refrigerator model and two car ECU (Electrical Control Unit) models are used to evaluate the performance of the proposed algorithm..