• Transactions on Semiconductor Engineering
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• v.2 no.4
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• pp.69-77
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• 2024

This paper presents that the SLH-DSA, a next-generation post-quantum cryptography, was designed as a hardware accelerator using High-Level Synthesis (HLS), implemented in the FPGA, and the performance analysis results show its superiority. The optimization design of the SLH-DSA was carried out using HLS technology, and the hardware accelerator of the digital signature and verification system was designed. The implementation and simulation were carried out using the ZYNQ UltraScale+ MPSoC ZCU104 FPGA. Finally, as a result of comparing the performance of the SLH-DSA hardware accelerator implemented in the FPGA with the CPU-based implementation, the execution time of the algorithm improved by about 596%, demonstrating the effectiveness of hardware acceleration.