• Electronics and Telecommunications Trends
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• v.5 no.1
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• pp.55-70
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• 1990

SIMOX SOI is known to be one of the most useful technologies for fabrications of new generation ULSI devices. This paper describes the current status of SIMOX SOI technology for ULSI applications. The SIMOX wafer is vertically composed of buried oxide layer and silicon epitaxial layer on top of the silicon substrate. The buried oxide layer is used for the vertical isolation of devices The oxide layer is formed by high energy ion implantation of high dose oxygen into the silicon wafer, followed by high temperature annealing. SIMOX-based CMOS fabrication is transparent to the conventional IC processing steps without well formation. Furthermore, thin film CMOX/SIMOX can overcome the technological limitations which encountered in submicron bulk-based CMOS devices, i.e., soft-error rate, subthreshold slope, threshold voltage roll-off, and hot electron degradation can be improved. SIMOX-based bipolar devices are expected to have high density which comparable to the CMOX circuits. Radiation hardness properties of SIMOX SOI extend its application fields to space and military devices, since military ICs should be operational in radiation-hardened and harsh environments. The cost of SIMOX wafer preparation is high at present, but it is expected to reduce as volume increases. Recent studies about SIMOX SOI technology have demonstrated that the performance of the SIMOX-based submicron devices is superior to the circuits using the bulk silicon.

• Proceedings of the Materials Research Society of Korea Conference
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• 1999.11a
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• pp.73-73
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• 1999

• Journal of Sensor Science and Technology
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• v.3 no.1
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• pp.26-31
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• 1994

A SIMOX SOI Hall sensor has been fabricated and its characteristics were measured at temperatures between $20^{\circ}C$ and $260^{\circ}C$. Output Hall voltage varied linearly with supplied current, showing good linearity. The Hall voltage and the offset voltage initially increased slightly and then decreased with temperature due possibly to the electron mobility variation with temperature. Nearly constant product sensitivity throughout the temperature range indicates that this Hall sensor could be used for high temperature applications.

• Applied Microscopy
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• v.42 no.3
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• pp.151-157
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• 2012

The microstructure of various shapes of stacking fault pyramids (SFPs) formed in multiple implant/anneal Separation by Implanted Oxygen (SIMOX) material were investigated by plan-view and cross-sectional transmission electron microscopy. In the multiple implant/anneal SIMOX, the defects in the top silicon layer are confined at the interface of the buried oxide layer at a density of ${\sim}10^6\;cm^{-2}$. The dominant defects are perfect and imperfect SFPs. The perfect SFPs were formed by the expansion and interaction of four dissociated dislocations on the {111} pyramidal planes. The imperfect SFPs show various shapes of SFPs, including I-, L-, and Y-shapes. The shape of imperfect SFPs may depend on the number of dissociated dislocations bounded to the top of the pyramid and the interaction of Shockley partial dislocations at each edge of {111} pyramidal planes.

• Journal of the Korean Vacuum Society
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• v.4 no.4
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• pp.373-379
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• 1995

200keV의 에너지로 산소 이온들을 주입한 후 열처리하여 만든 SIMOX의 층구조를 분광 타원해석법을 이용하여 비파괴적으로 분석하여, 약 $300AA$의 계면층과 $800\AA$의 매몰산화층이 $3360\AA$ 정도의 결정성 실리콘층 아래에 존재하는 것을 알 수 있었다. 이러한 매몰산화층의 분포와 TRIM 전산시늉 결과의 비교로부터 매몰산화층의 형성은 산소 이온들이 열처리에 따라 이온 주입시 실리콘의 비정질화가 최대인 곳 주변으로 이동하여 이루어짐을 알 수 있었다. 또한 측정 위치에 따른 분광 타원해석 상수들의 변화로부터 이온주입시의 이온빔의 형태와 주사 방향의 영향으로 생긴 SIMOX층구조의 비균일성을 알 수 있었다.

• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.206-211
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• 1992

SIMOX SOI structures were formed by oxygen ion implantation with a dose of 2 1018 ions/cm2 at 180kev and post-implantation annealing at $1250^{\circ}C$ for 6 hours in nitrogen ambient. The oxygen redistribution process during post-implantation annealing was examined by AES and TEM. The electrical property of the structure was investigated by SRP method. We could find oxygen precipitates in SOI layer was discussed. And the limiting factor to the decrease of the precipitates during post-implantation annealing was discussed also.

• Proceedings of the Korean Vacuum Society Conference
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• 1992.02a
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• pp.93-94
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• 1992

2X1018 ions/cmz at 180 keV and post-implantation annealing at 12500C for 6 hours in nitrogen ambient. The oxygen redistribution process during post-implantation annealing was examined by AES and TEM. The electrical property of the structure was investigated by SRP method. We could find oxygen precipitates in SOl layer after high temperature annealing. The influence of the precipitates to the electrical property of the SOl layer was discussed. And the Iimiting factor to the decrease of the precipi tates during post-implantation anneal ing was discussed also.

• Proceedings of the Korean Vacuum Society Conference
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• 1996.06a
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• pp.91-91
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• 1996

• Journal of the Korean Vacuum Society
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• v.7 no.1
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• pp.35-42
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• 1998

- The Si-$SiO_2$ interface of silicon on insulator (SOI) formed by 100 keV $O^+$ was ohserved using high resolution transmission electron microscopy (HRTEM), before and after annealing. The interface of as-implanted sample, ~$5\times 10^{17}\textrm{cm}^{-2}O^+$ implanted at $550^{\circ}C$ was very rough and it has many defectsoxide precipitate, stacking fault, coesite $SiO_2$ etc. However, the interface became flat by high temperature annealing at $1300^{\circ}C$ for 4 hour. It's roughness, observed by HRTEM, was comparable to the interface roughness of 3 keV $O_2^\;+$ ion beam oxide and -6 nm gate oxide formed by thermal oxidation.

• ETRI Journal
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• v.9 no.1
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• pp.146-157
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• 1987

SOI(Silicon-On-Insulator)는 차세대 VLSI 구조로서 최근 중요한 연구개발 대상이 되고 있다. SOI의 제조기술을 크게 recrystallization, ELO, FIPOS 및 SIMOX로 나누고 이들 각 기술에 대한 고찰을 하였다. 향후 전반적인 SOI 제조기술 개발방향은 SOI면적 확장 및 결함 감소를 위한 것이 될 것이다.