• Title/Summary/Keyword: SD-ROM filter

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Adaptive Weighted Mean Filter to Remove Impulse Noise in Images (영상에서 임펄스 잡음제거를 위한 적응력 있는 가중 평균 필터)

  • Lee, Jun-Hee;Choi, Eo-Bin;Lee, Won-Yeol;Lim, Dong-Hoon
    • The Korean Journal of Applied Statistics
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    • v.21 no.2
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    • pp.233-245
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    • 2008
  • In this work, a new adaptive weighted mean filter is proposed for preserving image details while effectively suppressing impulse noise. The proposed filter is based on a noise pixel detection-estimation strategy. All the pixels are first detected using an impulse noise detector. Then the detected noise pixels are replaced with the output of the weighted mean filter over adaptive working window according to the rate of corrupted neighborhood pixels, while noise-free pixels are left unaltered. We compare the proposed filter to other existing filters in the qualitative measure and quantitative measures such as PSNR and MAE as well as computation time to verify the capability of the proposed filter. Extensive simulations show that the proposed filter performs better than other filters in impulse noise suppression and detail preservation without increasing of running time.

The Efficient Design Method Of ROM Accessed Address In Due Sequence (순차 주소 접근 ROM의 효율적인 설계 방법)

  • Kim, Yong-Eun;Kim, Kang-Jik;Cho, Seong-Ik;Chung, Jin-Gyun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.8
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    • pp.18-21
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    • 2009
  • In the digital system, ROM has a large power-consumption and a speed-bottleneck. According to gradual growth of system speed, ROM is demanded to have low-power consumption and high-speed operation design. The ROM adapted in FFT or FIR filter needs method of sequential accessed addressing. We proposed a reduction method for the number of storage cells in this paper. The number of storage cells which is connected with bi-line is reduced by the proposed method so that the capacitance value of bit-time is reduced. In this case, delay time, and power consumption are reduced. Design result of ROM in this paper using the proposed method could reduce up to 86.3% of storage cell '1' compare with conventional method.

Development and Implementation of Noise-Canceling Technology for Digital Stethoscope (디지털 청진기를 위한 잡음 제거 기술 개발 및 구현)

  • Lee, Keunsang;Ji, Youna;Jeon, Youngtaek;Park, Young Chool
    • Journal of Biomedical Engineering Research
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    • v.34 no.4
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    • pp.204-211
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    • 2013
  • In this paper, an algorithm for suppressing acoustic noises contained in stethoscope sound is proposed and implemented in real-time using an embedded DSP system. Sound collected by stethoscope is down-sampled and band-pass filtered, and later an NLMS adaptive filter is used to cancel the acoustic noise induced from external noise sources. Also, the unpredictable impulsive noises due to fabric friction and instantaneous tapping are detected using the SD-ROM algorithm, and suppressed using an algorithm approximating the morphology filter. The proposed algorithm was tested using signals collected with a digital stethoscope mockup, and implemented on an ARM920T-based DSP system.

The Optimal Extraction Method of Adder Sharing Component for Inner Product and its Application to DCT Design (내적연산을 위한 가산기 공유항의 최적 추출기법 제안 및 이를 이용한 DCT 설계)

  • Im, Guk-Chan;Jang, Yeong-Jin;Lee, Hyeon-Su
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.7
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    • pp.503-512
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    • 2001
  • The general DSP algorithm, like orthogonal transform or filter processing, needs efficient hardware architecture to compute inner product. The typical MAC architecture has high cost of silicon. Because of this reason, the distributed arithmetic without multiplier is widely used for implementing inner product. This paper presents the optimization to reduce required hardware in distributed arithmetic by using extraction method of adder sharing component. The optimization process uses Boltzmann-machine which is one of the neural network. This proposed method can solve problem that is increasing complexity depending on depth of inner product and compose optimal summation-network with the minimum FA and FF in a few time. The designed DCT by using Proposed method is more efficient than a ROM-based distributed arithmetic.

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