• Journal of Broadcast Engineering
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• v.19 no.3
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• pp.355-361
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• 2014

In this paper, we propose a complexity reduction method of sample adaptive offset (SAO), which is an in-loop filter in high-efficiency video coding (HEVC). In the conventional SAO, an offset value is calculated for each coding tree block (CTB) to minimize the error between the original and reconstructed images. In order to determine the optimal offset value, all offset candidates are examined and the offset value that leads to the smallest rate-distortion cost is chosen. Thus, SAO occupies a significant amount of the computational complexity in the HEVC encoder. In the proposed method, we determine the least-used band (LUB) by considering the statistical characteristics of offset values and without processing the offset value included in the LUB. Also, in the offset value decision stage, we check only a certain number of candidates rather than all of them. Experimental results show that the proposed method reduces the encoding time by approximately 8.15% without yielding a significant loss in terms of coding efficiency.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.07a
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• pp.468-470
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• 2012

본 논문에서는 High Efficiency Video Coding (HEVC)을 하드웨어로 구현하기 위해서 파이프라인 방식을 인-루프 필터에 새롭게 도입된 기술인 Sample Adaptive Offset (SAO)에 적용하여 병렬화 처리하는 방법을 제안한다. 현재 HEVC 에서 SAO 의 입출력이 프레임단위로 구현되어 있는데, 이를 파이프라인 방식의 하드웨어 설계시에는 Largest Coding Unit(LCU)단위로 입출력이 가능하도록 수정해야 한다. SAO 에서 사용하는 두 가지 방식으로 Edge Offset(EO)과 Band Offset(BO)모드가 있으며, 이 중 EO 모드가 주변 화소값을 이용하므로 주변 화소값 정보가 없는 LCU 경계에 위치한 화소들을 버퍼에 저장한 뒤, 다음 LCU 블록의 입력과 함께 SAO 를 수행한다. 또한, SAO 앞 단의 인-루프 필터 기술인 디블록킹 필터(Deblocking Filter)에서도 LCU 단위로 입출력이 수행되므로 디블록킹 필터에서 저장하는 버퍼를 고려하면, SAO 입력에서 사용가능한 데이터는 LCU 가 천이된 형태가 된다. 따라서 SAO 입력의 천이된 형태와 버퍼 사용에 따라 총 9 가지 타입을 갖게 되며, 이 중 경계에 위치한 블록을 제외한 타입들의 경우 서로 다른 정보를 가진 SAO 를 4 번 수행해야 한다. 이러한 점을 반영한 파이프라인 방식을 SAO 에 적용하여 하드웨어에 적합한 구조를 구현할 수 있다.

• Journal of Broadcast Engineering
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• v.17 no.3
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• pp.503-518
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• 2012

In this paper, we propose a complexity-based parallelization method of the sample adaptive offset (SAO) algorithm which is one of HEVC in-loop filters. The SAO algorithm can be regarded as region-based process and the regions are obtained and represented with a quad-tree scheme. A offset to minimize a reconstruction error is sent for each partitioned region. The SAO of the HEVC can be parallelized in data-level. However, because the sizes and complexities of the SAO regions are not regular, workload imbalance occurs with multi-core platform. In this paper, we propose a LCU-based SAO algorithm and a complexity prediction algorithm for each LCU. With the proposed complexity-based LCU processing, we found that the proposed algorithm is faster than the sequential implementation by a factor of 2.38 times. In addition, the proposed algorithm is faster than regular parallel implementation SAO by 21%.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.06a
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• pp.354-356
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• 2013

ITU와 ISO/IEC가 공동으로 UHD급 영상 부호화를 위해 표준화를 진행하고 있는 HEVC 코덱은 H.264/AVC 대비 2배 이상의 압축 효율을 갖는 것을 목표로 정하고 있다. HEVC(High Efficiency Video Coding)는 In-Loop Filter 기술로 H.264/AVC에서 사용하고 있는 Deblocking Filter와 새롭게 추가 된 SAO(Sample Adaptive Offset)를 사용하고 있다. 본 논문에서는 HEVC의 In-Loop Filter 기술 중 하나인 SAO의 기술의 EO에서 Category를 조금 더 정확하게 판단하여 분류하는 방법을 제안을 한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.645-648
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• 2012

본 논문에서는 고성능 HEVC(High Efficiency Video Coding) 복호기 설계를 위한 효율적인 SAO(Sample Adaptive Offset)의 하드웨어 구조 설계에 대해 기술한다. SAO는 양자화 등의 손실 압축에 의해 발생하는 정보의 손실을 보상하는 기술이다. 하지만 HEVC의 최대 블록 크기인 $64{\times}64$ 단위를 화소 단위 연산을 수행하기 때문에 높은 연산시간 및 연산량이 요구된다. 따라서 본 논문에서 제안하는 SAO 하드웨어 구조는 $8{\times}8$ 단위를 처리하는 연산기로 구성하여 하드웨어 면적을 최소화하였고, 내부레지스터를 이용하여 $64{\times}64$ 블록 크기를 지원한다. 또한 기존 SAO의 top-down 블록분할 구조에서 down-top 블록분할 구조로 설계하여 연산시간 및 연산량을 최소화 하였다. 제안하는 하드웨어 구조는 Verilog HDL로 설계하였으며, TSMC 칩 공정 $0.18{\mu}m$ 셀 라이브러리로 합성한 결과 동작 주파수는 250MHz, 전체 게이트 수는 45.4k 이다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.169-177
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• 2015

This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.271-274
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• 2014

This paper proposes high-performance SAO(Sample Adaptive Offset) in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. SAO is a newly adopted technique belonging to the in-loop filter in HEVC. The proposed SAO encoder hardware architecture uses three-layered buffers to minimize memory access time and to simplify pixel processing and also uses only adder, subtractor, shift register and feed-back comparator to reduce area. Furthermore, the proposed architecture consists of pipelined pixel classification and applying SAO parameters, and also classifies four consecutive pixels into EO and BO concurrently. These result in the reduction of processing time and computation. The proposed SAO encoder architecture is designed by Verilog HDL, and implemented by 180k logic gates in TSMC $0.18{\mu}m$ process. At 110MHz, the proposed SAO encoder can support 4K Ultra HD video encoding at 30fps in real time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.391-396
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• 2013

In this paper, for HEVC decoding, an SAO hardware design with less processing time and reduced area is proposed. The proposed SAO hardware architecture introduces the design processing $8{\times}8$ CU to reduce the hardware area and uses internal registers to support $64{\times}64$ CU processing. Instead of previous top-down block partitioning, it uses bottom-up block partitioning to minimize the amount of calculation and processing time. As a result of synthesizing the proposed architecture with TSMC $0.18{\mu}m$ library, the gate area is 30.7k and the maximum frequency is 250MHz. The proposed SAO hardware architecture can process the decode of a macroblock in 64 cycles.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.11a
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• pp.67-70
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• 2013

본 논문에서는 HEVC(high efficiency video coding)의 후처리 필터 중 하나인 적응적 샘플 오프셋(sample adaptive offset, SAO) 기술을 고속화 하는 방법을 제안한다. 기존의 SAO 는 원 영상과 복원된 영상간의 오차를 최소화하기 위해 각 블록마다 오프셋 값을 계산하므로 연산 복잡도가 매우 높다. 따라서 제안한 방법에서는 다양한 입력 영상에 대한 오프셋 사용빈도를 알아보고, 그 통계를 기반으로 불필요한 오프셋 연산을 생략한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.335-342
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• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.