• Journal of IKEEE
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• v.27 no.3
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• pp.220-224
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• 2023

Row hammering is a phenomenon in which bit flips occur in adjacent rows when accessing a particular row continuously, causing data damage, security problems, and poor computing performance. This paper analyzes the cause and response method of row hammering through TCAD simulation in 2ynm DRAM. In the experiment, the row hammering is reproduced while changing the parameters of the trap and the device structure, and the trap density, temperature. It analyzes the relationship with Active Wisdom, etc. As a result, it was confirmed that changes in trap parameters and device structures directly affect ΔV_cap/pulse. This enables a fundamental understanding of low hammering and finding countermeasures, and can contribute to improving the stability and security of DRAM.