• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.285-287
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• 2014

This paper describes a design of area-efficient/low-power cryptographic processor for lightweight block cipher algorithm HIGHT which was approved as a cryptographic standard by KATS and ISO/IEC. The HIGHT algorithm which is suitable for the security of IoT(Internet of Things), encrypts a 64-bit plain text with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we adopt 32-bit data path and optimize round transform block and key scheduler to share hardware resources for encryption and decryption.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.777-779
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• 2014

The LEA(Lightweight Encryption Algorithm) is a 128-bit high-speed/lightweight block cipher algorithm developed by National Security Research Institute(NSRI) in 2012. The LEA encrypts plain text of 128-bit using cipher key of 128/192/256-bit, and produces cipher text of 128-bit, and vice versa. To reduce hardware complexity, we propose an efficient architecture which shares hardware resources for encryption and decryption in round transformation block. Hardware sharing technique for key scheduler was also devised to achieve area-efficient and low-power implementation. The designed LEA cryptographic processor was verified by using FPGA implementation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.3
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• pp.485-494
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• 2012

The block cipher HIGHT is designed suitable for low-resource hardware implementation. It established as the TTA standard and ISO/IEC 18033-3 standard. In this paper, we propose a differentail fault attack against the block cipher HIGHT. In the proposed attack, we assume that an attacker is possible to inject a random byte fault in the input value of the 28-th round. This attack can recover the secret key by using the differential property between the original ciphertext and fault cipher text pairs. Using 7 and 12 error, our attack recover secret key within a few second with success probability 87% and 51%, respectively.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.1
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• pp.51-61
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• 2009

Conventional DES has been not only shown to have a vulnerable drawback to attack method called 'Meet in the Middle', but also to be hard to use that it is because software implementation has a number of problem in real time processing. This paper describes the design and implementation of the expanded DES algorithm using VHDL for resolving the above problems. The main reason for hardware design of an encryption algorithm is to ensure a security against cryptographic attack because there is no physical protection for the algorithm written in software. Total key length of 352 bits is used for the proposed DES. The result of simulation shows that the inputted plaintext in cryptosystem are equal to the outputted that in decryptosystem.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1495-1500
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• 2011

Dynamic cipher has the property that the key-size, the number of round, and the plain text-size are scalable simultaneously. In this paper we propose the block cipher algorithm which is symmetrical in the dynamic network. We present the method for designing secure Dynamic cipher against meet-in-the-middle attack and linear crytanalysis. Also, we show that the differential cryptanalysis to Dynamic cipher is hard.

• Proceedings of the Korea Contents Association Conference
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• 2009.05a
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• pp.510-514
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• 2009

This program was developed in Visual C + +, the Windows operating system has security features within the files and directories. File and directory security, encryption / decryption operations yirueojimyeo file security can be round, to know the value of the key and security password I need to know the directory is designed to be decrypted. In addition, ECB, CBC algorithm and 3DES, SEED algorithms and methods, and encryption. De0 can not run that created the file extension, as has been developed to allow for double security.

• Proceedings of the Korean Information Science Society Conference
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• 2007.10d
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• pp.261-266
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• 2007

UMTS release 5 에서 소개된 HSDPA 를 위해 도입된 새로운 기술 Adaptive Modulation and Coding, Hybrid Automatic Repeal reQuest, Fast Packet Scheduling 에 대해 알아보고 여기서 key role 이 되는 Fast Packet Scheduling 알고리즘 가운데 대표적인 세 가지 Round Robin(RR), Promotional Fairness(PF), Maximum Channel Quality Index(Max CQI) 알고리즘의 성능을 시스템 수율과 공평성의 관점에서 분석해보았다. 시스템 수율에서는 Max CQI, PF. RR 알고리즘 순이었으며 공평성 측면에서는 RR, PF Max CQI 알고리즘 순으로 나타났다. 같은 시스템, 같은 망 구조 내에서라면 알고리즘을 최적화하여 QoS와 성능을 극대화할 수 있도록 지속적인 연구가 필요하다.

• Proceedings of the Korea Concrete Institute Conference
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• 2009.05a
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• pp.109-110
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• 2009

This study is to evaluate the shear performance of joint between existing and new slab in apartment remodeling construction for enlarging existing slab. The horizontal joint parameters are consisted by steel pipe cotter, shear reinforcement, H-steel, stud bolt, and round shear key by concrete. And joint specimens will be tested to evaluate the shear performance of these parameters. If the joint detail have sufficient strength, it will be proposed the basic form on the design of joint parts.

• Journal of Power System Engineering
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• v.5 no.2
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• pp.57-62
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• 2001

Gas turbine performance is highly dependent on the engine performance which is closely related to the engine materials since they are exposed to severe working environments, i.e, high temperature and high stresses. For this reason, advanced materials with improved properties are required for the engine. The purpose of this research is to develop key materials technologies for aircraft industry and to tester domestic production of related parts. In this paper, the real-time prediction of high temperature creep strength and creep life for nickel-based superalloy Udimet 720(high-temperature and high-pressure the gas turbine engine materials) was performed on round-bar type specimens under pure load at the temperatures of 538, 649 and $704^{\circ}C$.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.9
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• pp.1652-1659
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• 2008

With the increase of huge amount of data in network systems, ultimate high-speed network has become an essential requirement. In such systems, the encryption and decryption process for security becomes a bottle-neck. For this reason, the need of hardware implementation is strongly emphasized. In this study, a mixed inner and outer round pipelining architecture is introduced to achieve high speed performance of ARIA hardware. Multiplexers are used to control the lengths of rounds for 3 types of keys. Merging of encryption module and key initialization module increases the area efficiency. The proposed hardware architecture is implemented on reconfigurable hardware, Xilinx Virtex2-pro. The hardware architecture in this study shows that the area occupied 6437 slices and 128 BRAMs, and it is translated to throughput of 24.6Gbit/s with a maximum clock frequency of 192.9MHz.