• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.1
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• pp.59-70
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• 2022

In this paper, we proposed an active fault tolerant control (AFTC) method for the position control of a quadrotor with complete loss of effectiveness of one motor. We obtained the dynamics of a quadrotor using Lagrangian equation without small angle assumption. For detecting the fault on a motor, we designed a fault detection module, which consists of the fault detection and diagnosis (FDD) module and the fault detection and isolation (FDI) module. For the FDD module, we designed a nonlinear observer that observes the states of a quadrotor based on the obtained dynamics. Using the observed states of a quadrotor, we designed residual signals and set the appropriate threshold values of residual signals to detect the fault. Also, we designed an FDI module to identify the fault location using the designed additional conditions. To make a quadrotor track the desired path after detecting the fault of a motor, we designed a fault tolerant controller based on the multiple sliding surface control (MSSC) technique. Finally, through simulations, we verified the effectiveness of the proposed AFTC method for a quadrotor with complete loss of effectiveness of one motor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.58-67
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• 2009

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.