• Science of Emotion and Sensibility
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• v.13 no.1
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• pp.207-214
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• 2010

The aim of this study was to investigate upper and lower limb muscle activity using EMG(electromyogram) sensors while walking and identify normal gait pattern using FSR(force sensing resistor) sensor. Fifteen college students participated in this study and their EMG and FSR signal were measured during stopping and walking trials. EMG signals from upper(pectoralis major and trapezius) and lower limbs(rectus femoris, biceps femoris, vastus medialis, vastus lateralis, semimembranosus, semitendinosus, soleus, peroneus longus, gastrocnemius medialis, and gastrocnemius lateralis) were obtained using the surface electrodes. FSR measured pressures on 8 areas of the sole of the foot during walking. EMG results showed that all muscle activities except for vastus lateralis and semimembranosus during walking had higher amplitudes than stopping. Additionally, muscle activities associated with stance and swing phase during walking were identified. Results on FSR showed that stance and swing phases were detected by FSR signals during a gait cycle. Eight gait phases－initial contact, loading response, mid stance, terminal stance, pre swing, initial swing, mid swing, and terminal swing- were classified.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.