• Journal of the Korean Society of Manufacturing Process Engineers
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• v.16 no.5
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• pp.78-84
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• 2017

Compared to other types of power, hydraulic energy is the most commonly used for heavy vehicles and ships because it has fewer location and space constraints, and its controllability can be maintained even under adverse conditions. Operators have controlled a main control valve of ship winches by pushing or pulling the lever, which is directly connected to the spool. However, because of the spatial arrangement, the importance of remote control valves has emerged. In this paper, experiments of the hysteresis characteristics were performed by analyzing the remote-control valve using a valve tester and RA2300. The validity was verified by comparing with the analytical model using SimulationX as the hydraulic analysis program. This study examined the effects of the spool's notch (Non, End-mill, and Spherical) and the effects of stiffness and pre-load of the spool spring on Spool stroke, open area, and hysteresis characteristics. It is considered possible to reduce the cost and the, trial and error process in designing remote-control valves in the future.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1934-1937
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• 2005

This paper proposes suitable gait generation for dynamic walking of biped robot with varying load in real time. Author proposes the relationship between ZMP(Zero Moment Point) and measurement from FSR(Force Sensing Register). Simplifying this relationship, it is possible to reduce the computational time and control the biped robot in real time. If the weight of the biped robot varies in order to move some object, then joint trajectories of the the biped robot must be changed. When some object is loaded on the biped robot in it's home position, FSRs can measure the variation of weight. Evaluating the relations between varying load and stable gait of the biped robot, it can walk adaptively. This relation enables the biped robot to walk properly with varying load. The simulation is also represented in this paper which shows proposed relationships.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.141-151
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• 1994

this paper describes the design and implementation of a RISC processor for embedded control systems. This RISC processor integrates a register file, a pipelined execution unit, a FPU interface, a memory interface, and an instruction prefetcher. Its characteristics include both single cycle executions of most instructions in a 2 phase 20 MHz frequency and the worst case interrupt latency of 7 cycles with the vectored interrupt handling that makes it possible to be applicable to the real time processing system. For efficient handling of multi-cycle instructions, data stationary hardwired control scheme equippedwith cycle counter was used. This chip integrates about 139K transistors and occupies 9.1mm$\times$9.1mm in a 1.0um DLM CMOS technology. The power dissipation is 0.8 Watts from a 5V supply at 20 MHz operation.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.33 no.3
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• pp.93-101
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• 2010

Regarding project management, many organizations have developed and distributed general project management knowledge systems, and application fields use the knowledge systems to apply the process suitable for characteristics of a project. This study suggests project management process models to apply to product development projects and introduces the application cases. This product development project management process model is composed of five top processes of initiation and preparation, planning, implementation management, control, and termination and transfer. The five processes are re-divided into 18 bottom processes. These processes are expressed as input, control, output, and mechanism by using the IDEF0 model. This model is applied to the new car development project of a Korean automobile company and introduces the cases, which shows a project charter, a work breakdown structure, a project schedule, a progress s-curve, a risk register, and a performance report.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.73-76
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• 2001

High-level synthesis generates a structural design that implements the given behavior and satisfies design constraints for area, performance, power consumption, packaging, testing and other criteria. Thus, high-level synthesis generates that register-transfer(RT) level structure from algorithm level description. High-level synthesis consist of compiling, partitioning, scheduling. In this paper, we proposed the efficient scheduling algorithm that find the number of the functional unit and scheduling into the minimum control step with silicon area resource constrained.

• Journal of the Korean Institute of Telematics and Electronics
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• v.7 no.2
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• pp.26-32
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• 1970

Among the various methods used for determining control system dynamics, the method using cross-correlation function seems useful if the white noise can be available as a test signal. In this paper, results are reported of a M-sequence generator which was built by means of IC shift register as it designed by the authors. This signal appears very useful and promises future applications in adaptive control systems.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.8 no.2
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• pp.64-71
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• 2009

In this paper, This thesis is cell phone for make CAS service be for hand joining broadcasting Create a way CAS Chip. PerSam issue card inside use Seed Key and algorithm make CID Key and record CAS Chip. PerSam member Card inside use Seed Key and algorithm make Subscriber Key after include Subscriber. Key CAS Chip for record CID Key register EMM. make CAS CHIP in accordance with issue CAS Chip. broadcast service entry be for hand treatment so make low bandwidth for joining massage and make increase a member.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.5
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• pp.116-124
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• 2012

In this paper, we propose an efficient lighting control system design for AVR based LSDM control. This paper, an efficient lighting control system design for LSDM control be design divided as the signal control part for I/O data bus and the timer/counter part for clock signal control according to operating conditions. LSDM control logic be optimization to PORTx and DDRx register by specifying the logical value of each bit for effective control signal processing. And, the LSDM control signal by lighting control program execution of ATmega128 be designed to be LSDM lighting control by control logic operating. In this paper, a proposed lighting control system were measured to power loss rate to proved the power loss reduction about lighting status of LSDM control logic by download the lighting control program to system through serial from host PC. As a measurement result, a proposed lighting control system than the existing lighting control system were proved to be effective to the overall power consumption reduction.

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.9
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• pp.894-898
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• 2009

In a post printing section of roll to roll printing systems, scratch problem is the major defects. The functional qualities such as conductivity, mobility could deteriorate because of the scratch defect. In general, the scratch of the printed pattern on the flexible substrate was induced from a contact between rolls and printed pattern in the post printing section. In this paper, for non-contacting transfer of a moving web, a mathematical tension model has been developed considering strain due to air floatation and the proposed mode has been validated by numerical simulation. Additionally, the correlation between floatation height and speed compensation to control the tension and register are investigated. On the basis of the proposed model, a guide line of speed control in R2R printing system is presented to guarantee the non-contact between rolls and R2R printed pattern on the flexible substrate.