• Journal of Digital Convergence
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• v.12 no.3
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• pp.269-275
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• 2014

The DAB system was designed to provide CD quality audio and data services for fixed, portable and mobile applications with the required BER below $10^{-4}$. However for the T-DMB system with the video service of MPEG-4 stream, BER should go down $10^{-8}$ by adding FEC blocks which consist of the Reed-Solomon (RS) encoder/decoder and convolutional interleaver/deinterleaver. In this paper we propose two types of turbo coded T-DMB system without altering the puncturing procedure and puncturing vectors defined in the standard T-DMB system for compatibility. One(Type 1) can replace the existing RS code, convolutional interleaver and RCPC code by a turbo code and the other one (Type 2) can substitute the existing RCPC code by a turbo code. Simulation results show that two new turbo coded systems are able to yield considerable performance gain after just 2 iterations. Type 2 system is better than type 1 but the amount of performance improvement is small.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.36-43
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• 2006

In this paper we present a new high-speed parallel multiplier for Performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the MOD operation part to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of MOD operation part have two AND gates and two XOR gates. Using these MOD operation parts, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the MOD operation parts with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI. Also, since this circuit has a low propagation delay time generated by the gates during operating process because of not use the memory elements in the inside of multiplier circuit, this multiplier circuit realizes a high-speed operation.