• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.11
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• pp.21-28
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• 1993

Decoding algorithm of noncyclic Reed-Solomon codes consists of four steps which are to compute syndromes, to find error-location polynomial, to decide error-location, and to solve error-values. There is a decoding method by which the computation of both error-location polynomial and error-evaluator polynimial can be avoided in conventional decoding methods using Euclid algorithm. The disadvantage of this method is that the same amount of computation is needed that is equivalent to solve the avoided polynomial. This paper considers the division method on polynomial on GF(2$^{m}$) systematically. And proposes a novel method to find error correcting polynomial by simple mathematical expression without the same amount of computation to find the two avoided polynomial. Especially. proposes the method which the amount of computation to find F (x) from the division M(x) by x, (x-1),....(x--${\alpha}^{n-2}$) respectively can be avoided. By applying the simple expression to decoding procedure on RS codes, propses a new decoding algorithm, and to show the validity of presented method, computer simulation is performed.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.37-43
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• 1999

Two-way addressing method has been proposed for efficient VLSI implementation of Euclidean calculation circuit for pipelined Reed-Solomon decoder. This new circuit is operating with single clock while exploiting maximum parallelism, and uses register addressing instead of register shifting to minimize the switching power. Logic synthesis shows the circuit with the new scheme takes 3,000 logic gates, which is about 40% reduction from the previous 5,000 gate implementation. Computer simulation also shows the power consumption is about 3mW. The previous implementation with multiple clock consumed about 5mW.

• Journal of Advanced Navigation Technology
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• v.16 no.2
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• pp.190-196
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• 2012

In this paper, we propose an improved error correction code in order to improve the performance of digital modems for HF data communications and verify the performance of the proposed scheme. The proposed scheme employs outer Reed-Solomon codes concatenated with inner convolutional codes. Numerical results show that the proposed system significantly improves the bit error rate performance compared to the conventional PACTOR-III modems. Hence, the proposed system can improve the bandwidth efficiency of digital modems for HF data communications.

• Journal of Internet Computing and Services
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• v.10 no.1
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• pp.1-9
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• 2009

In this paper, A pipeline structured-degree computationless modified Euclidean (PS-DCME) algorithm is proposed, which can be used for a RS(23,17) decoder for MB-OFDM system. PS-DCME algorithm requires a state machine instead of the degree computation and comparison circuits, so that the hardware complexity of the decoder can be reduced and high-speed decoder can be implemented. We have implemented a RS(23,17) decoder with PS-DCME using Verilog HDL and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 19,827.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.5
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• pp.861-868
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• 2001

In this paper, the performance of Reed Solomon(RS)/convolution리 concatenated codes and turbo code using semi random interleaver over the radio communication channel was analyzed. In the result, we proved that the performance of decoder was excellent as increase the interleaver size, constraint length, and iteration number. When turbo code using semi random interleaver and Hsiconvolutional concatenated codes was constant constraint length L=5, BER=10-4 , each value of $E_b/N_o$ was 4.5〔dB〕 and 2.95〔dB〕. Therefore, when the constraint length was constant, we proved that the performance of turbo code is superior to RS/Convolutional concatenated codes about 1.55〔dB〕 in the case of BER=10-4.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.549-552
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• 2003

In this paper, an efficient architecture of a versatile Reed-Solomon (RS) decoder is designed, where the message length k as well as the block length n can be variable. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm(MEA). A new architecture for the MEA is designed for variable values of error correcting capability t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive and the overclocking technique. The decoder can decode a codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications due to its versatility. A versatile RS decoder over GF(2$^{8}$ ) having the error-correcting capability of up to 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11A
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• pp.1803-1811
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• 2001

In this paper, Forward Error Correction(FEC) that is satisfied with ITU-T Recommendation J.83, Annex B(North American Data Over Cable Service Interface Specifications(DOCSIS) for Multimedia Cable Network System(MCNS)) is analyzed. The FEC consist of Reed-Solomon(RS) layer, interleaving layer, randomization layer, and trellis coded modulation(TCM) layer. The effects of quantization of input symbol and of trace-back depth in the Viterbi decoder are simulated over AWGN channels.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.882-885
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• 2010

In view of the severe energy constraint in sensor networks, it is important to use the error control scheme of the energy efficiently. In this paper, we presented FEC (Forward Error Correcting) codes in terms of their power consumption. One method of FEC is RS (Reed-Solomon) coding, which uses block codes. RS codes work by adding extra redundancy to the data. The encoded data can be stored or transmitted. It could have errors introduced, when the encoded data is recovered. The added redundancy allows a decoder to detect which parts of the received data is corrupted, and corrects them. The number of errors which are able to be corrected by RS code can determine by added redundancy. We could predict the lifetime of RS codes which transmitted at 32 byte a 1 minutes. RS(15, 13), RS(31, 27), RS(63, 57), RS(127,115), and RS(255,239) can keep the days of 138, 132, 126, 111, and 103 respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.7A
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• pp.503-511
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• 2012

In this paper, the performance analysis of telemetering method using delayed frame time diversity (DFTD) as the outer code and Reed-Solomon (RS) code as the inner code is described. DFTD is used to transmit a real-time frame together with a time-delayed frame which was saved in the memory during a defined period. The RS code as a kind of FEC (forward error correction) is serially concatenated with DFTD. This method was applied to the design of telemetry units that have been used for flight tests in a communication environment with deep fading. The data of the flight test for four cases with no applied code, with DFTD only, with the RS code only, and with both DFTD and the RS code are used to analyze the performance. The simulation for time-delay suggests the possibility that all frame errors can be removed. And the results of 12 flight tests show the performance superiority of this new method to compare with the RS code only.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.6B
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• pp.727-735
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• 2001

본 논문은 8-VSB Advanced Digital TV용으로 사용할 수 있도록 ATSC(Advanced Television Standard Committee)의 규약을 만족시키도록 구현한 Reed Solomon 디코더에 대하여 기술한다. 구현된 RS Decoder는 공유된 Tree 구조의 Arithmetic 블록을 사용하여 종래의 기술보다 더 효율적인 연산기 구조를 제안하였으며 빠른 에러 탐지와 정정 시간으로 인한 FIFO의 사용갯수와 Latency Time을 크게 감소시킨 개선된 구조를 제안한다. 일반적으로 2N+A만큼의 Latency Time과 FIFO 개수를 N+A 만큼으로 감소시켰다. 이 RS 디코더는 Verilog HDL로 설계되었고 Synopsys Design Compiler에 의해 합성되었다.