• 국제지역연구
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• 제14권1호
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• pp.129-153
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• 2010

이 글에서 다루고자 하는 주요 퍼즐은 '왜 영국은 19세기 말 ~ 20세기 초 기간 동안 다른 국가와 달리 초국적기업이 출현하는 일반 구조를 발전시키지 못했는가?'이다. 이에 대해 필자는 비록 완전한 대답은 아니지만 근본적으로 영국 사회의 속성을 보여주는 '사회적 구성(Social construction)'의 맥락에서 그 원인을 규명하고자 한다. 이러한 목적 하에 이 글은 사건을 둘러싼 행위자들의 이해관계와 (사건에 대한)통제력이 빚어내는 사건의 가치 상승효과를 고려한다. 이 글의 결론은 다음과 같다: 첫째, 영국 사회 내에 팽배해 있었던 산업자본주의에 대한 경멸과 대기업 및 초국적 기업 육성의 필요성에 대한 영국 정부의 불식, 그리고 신사적 지배층의 확산과 더불어 수반된 시티의 상업-금융 자본가들의 영향력 확대 등도 영국 기업의 초국적화를 가로막았다. 둘째, 영국의 정치적 지배구조와 경제구조의 토대는 지속과 변화를 동시에 보여주었다. 1850년 이래 영국 사회구조는 점진적으로 시티의 상업-금융 자본가들의 영향력이 강화되는 구도로 형상화되었다. 그리고 그 결과는 제조업체의 초국적화가 아닌 금융서비스업의 초국적화였다. 셋째, 영국 엘리트 집단들이 주도한 사회연결망의 형상은 단절과 연계로 구분되는 행위자들의 이해관계와 통제력을 통해 구성된다. 서로의 이익이 상호보완적이었던 것과 달리 통제력의 차원에서 초기에는 지주계급과 상업-금융 자본가들의 자발적 동기에 기반 한 의도된 연계가 형성되었으나 결국 통제력의 소유는 산업자본가들을 배제한 채 상업-금융자본가들에게로 이전되어 사회연결망의 재구축이 이루어졌다.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}