• 제목/요약/키워드: Reconfigurable Structure

검색결과 98건 처리시간 0.026초

Cooperative Coordination Method of Neural Network Controller Module for Autonomous Mobile Robot Navigation

  • Joo, Han-Seong;Young, Oh-Se
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2001년도 ICCAS
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    • pp.178.3-178
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    • 2001
  • This paper is concerned with designing a neural network based navigator that is optimized in a user-defined sense for a mobile robot using ultrasonic sensors to travel to a goal position safely and efficiently without any prior map of the environment. The neural network has a dynamically reconfigurable structure that not only can optimize the weights but also the input sensory connectivity in order to meet any user-defined objective. Therefore, in this research, we can select an optimal subset of sensory inputs that results in the best performance related to both navigation and structural complexity. Further, this research uses the manually trained initial population and the modular neural network to alleviate ...

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Design of Reconfigurable Flight Controller Using Discrete Model Reference Adaptive Scheme

  • Hyung, Seung-Yong;Kim, You-Dan
    • International Journal of Aeronautical and Space Sciences
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    • 제8권1호
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    • pp.79-86
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    • 2007
  • In this paper, an adaptive control algorithm using system identification is proposed for an aircraft fault tolerant control system. A discrete state-space system is reformulated to be the ARX model which has the advantage in handing variable structure systems. Discrete model reference adaptive control is used to make the output of fault system follow the output of reference model. To validate the performance of the proposed control scheme, numerical simulations are performed for the high performance aircraft with control surface damage.

유전자 프로그래밍 기반의 하드웨어 진화 기법 (Hardware Evolution Based on Genetic Programming)

  • 석호식;이강;장병탁
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1999년도 하계종합학술대회 논문집
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    • pp.452-455
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    • 1999
  • We introduce an evolutionary approach to on-line learning for mobile robot control using reconfigurable hardware. We use genetic programming as an evolutionary engine. Control programs are encoded in tree structure. Genetic operators, such as node mutation, adapt the program trees based on a set of training cases. This paper discusses the advantages and constraints of the evolvable hardware approach to robot learning and describes a FPGA implementation of the presented genetic programming method.

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저전력/유연성 Uniform 필터 뱅크 구현을 위한 블록 필터 구조 (Block Filter Structure for Low-power/Reconfigurable Uniform Filter Banks Implementation)

  • 장영범;양세정
    • 한국통신학회논문지
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    • 제26권6B호
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    • pp.752-759
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    • 2001
  • 본 논문은 필터 뱅크의 저전력 구조와 유연성 구조를 위한 구현 방법을 제안한다. 이와 같은 특성을 갖도록 하기 위하여 블록 필터를 필터 뱅크에 사용하였다. 블록 필터를 데시메이션 필터에 적용함으로써, 블록 필터의 병렬-직렬 변화기와 다운 샘플러가 상쇄됨을 보인다. 인터폴레이션 필터에서도 마찬가지로, 업 샘플러와 블록 필터의 직렬-병렬 변환기가 상쇄되어 효율적인 구조가 만들어짐을 보인다. 더 나아가, 블록 필터를 Uniform 필터 뱅크에 적용함으로써 분석 단자 합성 단의 첫 번째 채널 필터가 모든 채널에 공유될 수 있음을 보인다. 이와 같은 공유를 통하여 계산량이 현저히 감소된 필터 뱅크를 구현할 수 있었다. 또한 블록 필터 뱅크는 필터 뱅크의 차수 변환에 따른 하드웨어의 가감이 매우 용이하여 유연성을 갖는 구조임을 보인다.

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진보된 멀티미디어 프로세서 구조 (Advanced Multimedia Processor Architecture)

  • 박춘명
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2013년도 추계학술대회
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    • pp.664-665
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    • 2013
  • 본 논문에서는 멀티미디어프로세서 구성의 한가지 방법을 제안하였다. 제안한 멀티미디어프로세서는 각각의 문자, 소리, 비디오를 한 개의 칩안에서 다룰 수 있으며, 멀티미디어의 특징인 인터렉티브의 기능을 갖고 있다. 특히 제안한 멀티미디어프로세서는 소프트웨어 없이도 메모리매상의 어드레싱이 가능하다. 제아난 멀티미디어프로세서는 가상현실에 적용이 가능하다.

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A Study on Embodiment of Evolving Cellular Automata Neural Systems using Evolvable Hardware

  • Sim, Kwee-Bo;Ban, Chang-Bong
    • 한국지능시스템학회논문지
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    • 제11권8호
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    • pp.746-753
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    • 2001
  • In this paper, we review the basic concept of Evolvable Hardware first. And we examine genetic algorithm processor and hardware reconfiguration method and implementation. By considering complexity and performance of hardware at the same time, we design genetic algorithm processor using modularization and parallel processing method. And we design frame that has connection structure and logic block on FPGA, and embody reconfigurable hardware that do so that this frame may be reconstructed by RAM. Also we implemented ECANS that information processing system such as living creatures'brain using this hardware reconfiguration method. And we apply ECANS which is implemented using the concept of Evolvable Hardware to time-series prediction problem in order to verify the effectiveness.

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진화형하드웨어 설계에 관한 연구 (A Study on the Evolvable Hardware Design (EHW))

  • 김종오;김덕수;이원석
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2007년도 하계종합학술대회 논문집
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    • pp.449-450
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    • 2007
  • Evolvable hardware(EHW) is a dynamic field that brings together reconfigurable hardware, artificial intelligence, fault tolerance and autonomous systems. This paper gives an introduction to the field. The features that can be used to identify and classify evolvable hardware are the evolutionary algorithm, the implementation and the genotype representation. Evolvable hardware (EHW) is hardware that can change its own circuit structure by genetic learning to achieve maximum adaptation to the environment. In conventional EHW, the learning is executed by software on a computer.

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다이버시티 안테나의 소형화와 격리도 향상을 위한 미앤더 선로와 개방형 루프가 결합된 방사구조의 설계 (Design of the Open-Loop Combined Meandered-Line 1-Layer Radiator for Diversity Antennas with Size-Reduction and Improved Isolation)

  • 목세균;강승택;김용진
    • 전기학회논문지
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    • 제61권1호
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    • pp.110-116
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    • 2012
  • This paper proposes a new diversity antenna which is the base of MIMO, tunable and reconfigurable antennas. The antenna has a small size and high inter-antenna isolation resulting from the compact radiating element comprising a meandered line and an open-loop combined in one limited uniplanar space and a modified T-shaped decoupling structure, respectively. In a WiMAX band, the radiating element and the entire antenna are $0.092{\lambda}$ and $0.2216{\lambda}$ in size, which shows effective size-reduction and the gain and efficiency of the proposed antenna attached to the ground of a handheld device are 3.7dBi and 56% acceptable to the industrial standard.

Numerical Study to Design an Optical Node for Metropolitan Networks

  • Lee, Jong-Hyung
    • International Journal of Internet, Broadcasting and Communication
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    • 제11권4호
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    • pp.43-48
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    • 2019
  • We design a reconfigurable optical node for metropolitan WDM networks, and numerically study the capability of the node in the optical signal level. Unlike a long-haul WDM system, major limitations of metropolitan WDM systems are power loss, fiber dispersion and optical signal-to-noise ratio(OSNR) degradation due to EDFAs. Therefore, we include the behaviors of transmitter and receiver, and fiber, EDFAs, and optical filters(MUX/DeMux) in numerical simulations with varying parameters over wide range. From simulation results, we can identify the maximum span numbers for OC-48 and OC-192 to achieve $BER<10^{-12}$ using the node structure at various received powers and residual dispersions.

A Novel Scalable and Storage-Efficient Architecture for High Speed Exact String Matching

  • Peiravi, Ali;Rahimzadeh, Mohammad Javad
    • ETRI Journal
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    • 제31권5호
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    • pp.545-553
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    • 2009
  • String matching is a fundamental element of an important category of modern packet processing applications which involve scanning the content flowing through a network for thousands of strings at the line rate. To keep pace with high network speeds, specialized hardware-based solutions are needed which should be efficient enough to maintain scalability in terms of speed and the number of strings. In this paper, a novel architecture based upon a recently proposed data structure called the Bloomier filter is proposed which can successfully support scalability. The Bloomier filter is a compact data structure for encoding arbitrary functions, and it supports approximate evaluation queries. By eliminating the Bloomier filter's false positives in a space efficient way, a simple yet powerful exact string matching architecture is proposed that can handle several thousand strings at high rates and is amenable to on-chip realization. The proposed scheme is implemented in reconfigurable hardware and we compare it with existing solutions. The results show that the proposed approach achieves better performance compared to other existing architectures measured in terms of throughput per logic cells per character as a metric.