• 전기전자학회논문지
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• 제23권4호
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• pp.1337-1342
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• 2019

자동 한국 번호판 인식 (AKLPR)은 많은 분야에서 사용된다. 이러한 응용 분야에서 ALPR은 높은 인식률과 빠른 처리 속도가 중요하다. 최근 딥러닝의 발전으로 객체 감지 및 인식의 정확도와 속도가 향상 되고 있으며, 그 결과 딥러닝이 ALPR에 적용되고 있다. 특히 합성곱신경망(Convolutional Neural Network) 기반 객체 검출기가 ALPR에 적용되었다. 이러한 ALPR은 LP 영역을 검출하는 단계와 LP 영역의 문자를 검출 및 인식하는 단계로 구분되며, 각 단계는 별도의 CNN으로 구현된다. 본 논문에서는 단일 단계 CNN으로 ALPR을 구현하는 아키텍처를 제안한다. 제안하는 방법은 높은 인식률을 유지하면서 빠른 속도로 번호판 문자를 인식한다.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2002년도 춘계학술대회 논문집
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• pp.522-529
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• 2002

In this Paper, it has a proposal of the RFID(RFID : Radio Frequency Identification) system for high-speed recognition between the tag attached a mobile object moving high-speed and the static reader. It used 13.56MHz frequency at ISM band, and designed a reader in order to recognize a mobile object moving high-speed. It will be expected that RFID system enables a smooth railway signal control applying in railway system through the cyclic loop antenna.

• 한국멀티미디어학회논문지
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• 제11권6호
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• pp.787-795
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• 2008

Human recognition on camera is an interesting topic in computer vision. While fingerprint and face recognition have been become common, gait is considered as a new biometric feature for distance recognition. In this paper, we propose a gait recognition algorithm based on the knee angle, 2 feet distance, walking velocity and head direction of a person who appear in camera view on one gait cycle. The background subtraction method firstly use for binary moving object extraction and then base on it we continue detect the leg region, head region and get gait features (leg angle, leg swing amplitude). Another feature, walking speed, also can be detected after a gait cycle finished. And then, we compute the errors between calculated features and stored features for recognition. This method gives good results when we performed testing using indoor and outdoor landscape in both lateral, oblique view.

• 전기전자학회논문지
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• 제17권3호
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• pp.241-247
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• 2013

This paper presents the design of a System on Programmable Chip (SoPC) based on Field Programmable Gate Array (FPGA) for speech recognition in which Mel-Frequency Cepstral Coefficients (MFCC) for speech feature extraction and Vector Quantization for recognition are used. The implementing process of the speech recognition system undergoes the following steps: feature extraction, training codebook, recognition. In the first step of feature extraction, the input voice data will be transformed into spectral components and extracted to get the main features by using MFCC algorithm. In the recognition step, the obtained spectral features from the first step will be processed and compared with the trained components. The Vector Quantization (VQ) is applied in this step. In our experiment, Altera's DE2 board with Cyclone II FPGA is used to implement the recognition system which can recognize 64 words. The execution speed of the blocks in the speech recognition system is surveyed by calculating the number of clock cycles while executing each block. The recognition accuracies are also measured in different parameters of the system. These results in execution speed and recognition accuracy could help the designer to choose the best configurations in speech recognition on SoPC.

• Journal of Information Processing Systems
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• 제16권1호
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• pp.224-237
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• 2020

Recognition of banknote serial number is one of the important functions for intelligent banknote counter implementation and can be used for various purposes. However, the previous character recognition method is limited to use due to the font type of the banknote serial number, the variation problem by the solid status, and the recognition speed issue. In this paper, we propose an aspect ratio based character region segmentation and a convolutional neural network (CNN) based banknote serial number recognition method. In order to detect the character region, the character area is determined based on the aspect ratio of each character in the serial number candidate area after the banknote area detection and de-skewing process is performed. Then, we designed and compared four types of CNN models and determined the best model for serial number recognition. Experimental results showed that the recognition accuracy of each character was 99.85%. In addition, it was confirmed that the recognition performance is improved as a result of performing data augmentation. The banknote used in the experiment is Indian rupee, which is badly soiled and the font of characters is unusual, therefore it can be regarded to have good performance. Recognition speed was also enough to run in real time on a device that counts 800 banknotes per minute.

• 전자공학회논문지B
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• 제29B권10호
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• pp.69-77
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• 1992

Pattern Recognition is one of the fundamental areas of computer vision. The recognition of patterns with varying size and severe defects is especially important. However, it is known that the conventional algorithms such as GHT or structural approaches have limitations in speed and accuracy. In this paper, in order to avoid above-mentioned problems, we propose a new recognition algorithm which exploits the histogram of contour directions and the sampled spot matching method. While the former provides little influence against size variation, the latter has strong immunity to noise and defects. We applied those proposed algorithms for the recognition of numbers extracted from the car number plates and shapes of aircraft. Experimental result shows that it is possible to solve above-mentioned problems by complementary uses of those two suggested algorithms. The contour directional histogram method resulted in high-speed of average 0.013 sec/char and 0.1 sec/aircraft-image on IBM-386. The accuracy of recognition is as high as 99%. Sampled spot matching method has less speed than the former one, however, it showed fairly strong immunity to noise and defects.

• 전자공학회논문지B
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• 제32B권11호
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• pp.1527-1535
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• 1995

This paper introduces an isolated word recognition system realized on a neurocomputer called E-MIND II, which is a 2-D torus wavefront array processor consisting of 256 DNP IIs. The DNP II is an all digital VLSI unit processor for the EMIND II featuring the emulation capability of more than thousands of neurons, the 40 MHz clock speed, and the on-chip learning. Built by these PEs in 2-D toroidal mesh architecture, the E- MIND II can be accelerated over 2 Gcps computation speed. In this light, the advantages of the E-MIND II in its capability of computing speed, scalability, computer interface, and learning are especially suitable for real time application such as speech recognition. We show how to map a TDNN structure on this array and how to code the learning and recognition algorithms for a user independent isolated word recognition. Through hardware simulation, we show that recognition rate of this system is about 97% for 30 command words for a robot control.

• IEIE Transactions on Smart Processing and Computing
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• 제4권4호
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• pp.237-250
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• 2015

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries' speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but high-performance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

• International Journal of Control, Automation, and Systems
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• 제2권2호
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• pp.201-206
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• 2004

Counters for the various kinds of banknotes require high-speed distinctive point extraction and recognition. In this paper we propose a new point extraction and recognition algorithm for Euro banknotes. For distinctive point extraction we use a coordinate data extraction method from specific parts of a banknote representing the same color. To recognize banknotes, we trained 5 neural networks. One is used for inserting direction and the others are used for face value. The algorithm is designed to minimize recognition time by using a minimal amount of recognition data. The simulated results show a high recognition rate and a low training period. The proposed method can be applied to high speed banknote counting machines.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.1055-1056
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• 2008

In this paper, we survey various Robust Object Recognition Algorithms. One of the core technologies for local feature detector is Scale Invariant Feature Transform. And we compared several algorithms with SIFT based on IPP technology. As a result, the conversion of source codes using IPP is sped up. And this will be more improved recognition speed using SIMD Instructions.