• Journal of Convergence for Information Technology
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• v.9 no.1
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• pp.136-141
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• 2019

In this paper, we describe the design of a small size data acquisition system with STM32 processor based on Cortex-M4. The system is used for the sensor devices to collect raw data on production lines at factory and send them to the server computer in real time. Also the system is designed to easily acquisite various kinds of data collected from various sensors with the digital signal input unit, the analog signal input unit, the digital signal output unit and the analog signal output unit This small data acquisition system will contribute to the improvement of the quality of precision products in the industrial field by collecting various data in real time and transmitting data at high speed.

• The KIPS Transactions:PartA
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• v.14A no.7
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• pp.421-434
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• 2007

Among many other CG generated natural scenes, the representation of ocean surfaces is one of the most complicated and time-consuming problem because of its large extent and complex surface movement. We present a hybrid method to represent and animate unbound deep-water ocean surfaces by utilizing graphics processor as both simulation and rendering core. Our technique is mainly based on spectral approaches that generate a high-detailed height field using Fourier transform on a 2D regular grid. Additionally, we incorporate Gerstner model and generate low-detailed height field on a 2D projected grid in order to represent large waves and main structure of ocean surface. There is no interruption between CPU and GPU, and no need to transfer simulation results from the system memory to graphics hardware because the entire simulation and rending processes are done on graphics processor. As a result we can synthesize and render realistic water surfaces in real-time. Proposed techniques are readily adoptable to real-time applications such as computer games that have heavy work load on CPU but still demand plausible natural scenes.

• Journal of the Korea Society of Computer and Information
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• v.10 no.5 s.37
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• pp.313-322
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• 2005

In this paper, we implement and verify performance monitor for parallel signal processing system, using DSP Starter Kit(DSK) of which the basic Processor is TMS302C6711 chip. The key ideas of this performance monitor is, using Real Time Data Exchange(RTDX) for the Purpose of real-time data transfer and function of DSP/BIOS, the ability to measure the Performance measure like DSP workload, memory usage, and bridge traffic. In the simulation, FFT, 2D FFT, Matrix Multiplication, and Fir Filter, which are widely used DSP algorithms, have been employed. Using performance monitor and Code Composer Studio from Texas Instrument(Tl) , the result has been recorded according to different frequencies, data sizes, and buffer sizes for a single wave file. The accuracy of our performance monitor has been verified by comparing those recorded results.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2007.11a
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• pp.253-256
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• 2007

The web server for the embedded Linux system(ELS), unlike the ones for the usual Linux or Windows, has some disadvantages such as small number of installable applications, low compatibility and limited extensibility. This fact raises some problems when data are transferred in real-time via the web server, which are mainly caused by a poor performance of the processor and small-sized memory. Conventional user interfaces adopted for the usual web servers are unsuitable for the ELS because they are platform-limited and their installations are done by the form of plug-ins. If the web server for the ELS has an Ajax engine that can be utilized without any installation procedure, the advantages of usability, accessibility and quick response time can be obtained. This paper presents the Ajax interface for the ELS web server. The efficiency of the proposed technology in the real-time remote monitoring is shown through an implementation.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.7
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• pp.1025-1035
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• 1995

In this paper, we realize a real time digital FM synthesizer based on genetic algorithm using a general purpose digital signal processor. Especially, we synthesize diverse music sounds nicely using a synthesis model consisting of a single modulator and multiple carriers. Also we present genetic algorithm-based technique which determines optimal parameters for reconstruction through FM synthesis of a sound after analyzing the spectrum of PCM data as a standard music sound using FFT. Using the suggested parameter extractiuon algorithm, we extract parameters of several instruments and then synthesize digital FM sounds. To verify the validity of the parameter extraction algorithm as well as realization of a real time digital music synthesizer, the evaluation is first done by listening the sound directly as subjective test. Secondly, to evaluate the synthesized sound objectively with an engineering sense, we compare the synthesized sound with an original one in a time domain and a frequency domain.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.3
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• pp.77-85
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• 2009

Execution times of tasks can be variable depend on input data. If we choose a high performance processor to satisfy the worst case execution times, the hard cost becomes high and the energy consumption also becomes large. To apply a lower performance processor, we have to utilize processor capacity maximally while overrunning tasks can not affect deadlines of other tasks. To be used for such systems, this paper presents SBP (Shared Bandwidth Partitioning) that a processor bandwidth is reserved and shared among all tasks. If a task needs more processor capacity, it can use a portion of the shared bandwidth. A simulation result shows that SBP provides better performance than previous algorithms. SBP reduces deadline miss ratio which is related to scheduling quality. And the number of context switches, which is related to system overhead, is also reduced.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.697-700
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• 1988

This paper describes the design of a hardware system for ECG feature extraction based on pipeline processor consisting of three computers. ECG data is acquisited by 12 bit A/D converter with hardware QRS triggred detector. Four diagnostic parameters-heart, axis, and ST axis, and ST segment are used for the classification and the diagnosis of arrhythmia. The functions of the main CPU were distributed and processed with three microcomputers. Therefore the effective data process and the real time process using microcomputer can be obtained. The interconnection structure consisting of two common memory units is designed to decrease the delay time caused by data transfer between processors and designed by which the delay time can be taken 1% of one clock period.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.56-70
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• 2010

Rendering technique generating 2 dimensional image to give reality and high performance graphical processor for efficient processing of massive data are necessary to support realistic 3 dimensional graphical image. Recently, graphical hardwares have evolved rapidly. This enables high quality rendering effect that we were unable to process in realtime. Improving shading technique enabled us to render realistic images but still much time is required for this process. Multiple operational units are being integrated in a graphical processor for effective floating point operation using massive data to process almost real looking images. In this paper, we have designed and implemented a special functional unit to support high quality 3 dimensional computer graphic image on programmable integrated shader processor. We have done evaluation through functional level simulation of designed special functional unit. Hardware resource usage rate and execution speed are measured implementing directly on FPGA Virtex-4(xc4vlx200).

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.3
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• pp.527-534
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• 2023

Triple modular redundancy (TMR) systems can continue their mission by virtue of their structural redundancy even if one processor is attacked by faults. In this paper, we propose a new fault tolerance strategy by introducing checkpoints into the TMR system in which data saving and fault detection processes are separated while they corporate together in the conventional checkpoints. Faults in one processor are tolerated by synchronizing the state of three processors upon detecting faults. Simultaneous faults occurring to more than one processor are tolerated by re-executing the task from the latest checkpoint. We propose the checkpoint placement and fault detection strategy to maximize the probability of successful execution of a task within the given deadline. We develop the Markov chain model for the TMR system having the proposed checkpoint strategy, and derive the optimal fault detection and checkpoint interval.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.2 no.2
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• pp.133-138
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• 2002

In this paper, we propose an integrated GUI environment of parallel fuzzy inference system fur pattern classification of remote sensing data. In this, as 4 fuzzy variables in condition part and 104 fuzzy rules are used, a real time and parallel approach is required. For frost fuzzy computation, we use the scan line conversion algorithm to convert lines of each fuzzy linguistic term to the closest integer pixels. We design 4 fuzzy processor unit to be operated in parallel by using FPGA. As a GUI environment, PCI transmission, image data pre-processing, integer pixel mapping and fuzzy membership tuning are considered. This system can be used in a pattern classification system requiring a rapid inference time in a real-time.