• Title/Summary/Keyword: Ratioed circuit

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Accuracy Enhancement Technique in the Current-Attenuator Circuit (전류 감쇠 조정 회로에서의 정밀도 향상 기술)

  • Kim, Seong-Kweon
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.19 no.8
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    • pp.116-121
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    • 2005
  • To realize the tap coefficient of a finite impulse response(FIR) filter or the twiddle factor of a fast Fourier transform(FFT) using a current-mode analog circuit, a high accurate current-attenuator circuit is needed This paper introduces an accuracy enhancement technique in the current-mode signal processing. First of all, the DC of set-current error in a conventional current-attenuator using a gate-ratioed orient mirror circuit is analyzed and then, the current-attenuator circuit with a negligibly small DC offset-current error is introduced. The circuit consists of N-output current mirrors connected in parallel with me another. The output current of the circuit is attenuated to 1/N of the input current. On the basis of the Kirchhoff current law, the current scale ratio is determined simply by the number of the current mirrors in the N-current mirrors connected in parallel. In the proposed current-attenuator circuit the scale accuracy is limited by the ac gain error of the current mirror. Considering that a current mirror has a negligibly small ac gain error, the attainable maximum scale accuracy is theoretically -80[dB] to the input current.

Design of CMOS Dual-Modulus Prescaler and Differential Voltage-Controlled Oscillator for PLL Frequency Synthesizer (PLL 주파수 합성기를 위한 dual-modulus 프리스케일러와 차동 전압제어발진기 설계)

  • Kang Hyung-Won;Kim Do-Kyun;Choi Young-Wan
    • 한국정보통신설비학회:학술대회논문집
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    • 2006.08a
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    • pp.179-182
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    • 2006
  • This paper introduce a different-type voltage-controlled oscillator (VCO) for PLL frequency synthesizer, And also the architecture of a high speed low-power-consumption CMOS dual-modulus frequency divider is presented. It provides a new approach to high speed operation and low power consumption. The proposed circuits simulate in 0.35 um CMOS standard technology.

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