• Proceedings of the Korea Contents Association Conference
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• 2010.05a
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• pp.366-370
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• 2010

로봇 기술이 발달하면서 사람의 지령에 의해 수동적, 반복적인 작업을 수행하던 기존 전통적 로봇에서 벗어나, 스스로 외부환경을 인식하고, 상황을 판단하여 자율적으로 동작하는 지능형 로봇이 등장하였다. 이러한 로봇의 S/W개발은 편의성을 위해 범용 운영체제를 사용하여 개발하는 추세이다. 지능형 서비스의 QoS(Quality of Service)를 위해서는 로봇 미들웨어에 실시간성을 지원해야 하지만 범용 운영체제는 실시간성을 지원하지 않는 문제점이 있다. 본 논문에서는 범용 운영체제인 오픈솔라리스에 실시간성을 위한 논리적 정확성 및 시간 결정성을 보장하기 위하여 실시간 스케쥴러를 포함한 실시간 프레임 워크 RTL(Real-Time Layer)을 설계 및 구현한 내용을 기술한다. 또한 성능측정을 위해 쓰레드의 응답시간을 측정하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.106-114
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• 2010

We proposed an unified design methodology and verification platform for giga-scale System on Chip (SoC). According to the growth of VLSI integration, the existing RTL design methodology has a limitation of a production gap because a design complexity increases. A verification methodology need an evolution to overcome a verification gap. The proposed platform includes a high level synthesis, and we develop a power-aware verification platform for low power design and verification automation using it's results. We developed a verification automation and power-aware verification methodology based on control and data flow graph (CDFG) and an abstract level language and RTL. The verification platform includes self-checking and the coverage driven verification methodology. Especially, the number of the random vector decreases minimum 5.75 times with the constrained random vector algorithm which is developed for the power-aware verification. This platform can verify a low power design with a general logic simulator using a power and power cell modeling method. This unified design and verification platform allow automatically to verify, design and synthesis the giga-scale design from the system level to RTL level in the whole design flow.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.883-886
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• 2003

본 논문에서는 Lifting-Based Scheme을 이용한 DWT(Discrete Wavelet Transform) 의 개선된 행 처리기의 구조를 제안 하였다. 제안된 행 처리기는 3개의 Adder 와 2개의 shifter를 사용 하였고 dual-port RAM을 사용하여 파이프 라인 구조를 취하여 각 클럭마다 열처리기에서 사용할 데이터를 발생 한다. 이러한 행 처리기의 파이프 라인 구조를 개선하여 Adder를 줄이고 행 처리기의 이용률을 최대로 하여 하드웨어의 공간적 비용 절감 효과를 가져 왔다. 제안된 구조는 Verilog를 사용하여 RTL설계를 한뒤 시뮬레이션으로 그 동작을 확인 하였다.

• Journal of Broadcast Engineering
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• v.24 no.3
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• pp.485-494
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• 2019

A software-driven real-time frequency de-modulator is implemented with the aid of universal-serial-bus (USB) type software defined radio dongle. An analog stereo frequency modulation (FM) broadcast signal is down-converted to the basedband analog signal then converted to digital bit streams in the USB dongle. Computer software such as Matlab, Python, and GNU Radio manipulates the incoming bit streams with the technique of digital signal processing. Low pass filtering, band pass filtering, decimation, frequency discriminator, double sideband amplitude demodulation, phase locked loop, and deemphasis function blocks are implemented using such computer languages. Especially, GNU Radion is employed to realize the real-time demodulator.

• The Magazine of the IEIE
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• v.30 no.9
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• pp.1002-1011
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• 2003

In this paper, we introduce an integrated SoC front-end design & verification environment which can be practically used in the embedded 32-bit processor-core SoC VLSI design. Our introduced SoC design & verification environment integrates two most important flows, such as the RTL power estimation and code coverage analysis, with the functional verification (chip validation) flow which is used in the conventional simulation-based design. For this, we developed two simulation-based inhouse tools, RTL power estimator and code coverage analyzer, and used them to adopt them to our RTL design and to increase the design quality of that. Our integrated design environment also includes basic design and verification flows such as the gate-level functional verification with back annotation information and test vector capture & replay environment.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.50-56
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• 2016

This paper proposes the architecture and design of intra prediction circuit for a multi-decoder supporting UHD images. The proposed circuit supports not only the latest video compression standard HEVC but also H.264. In addition to the basic function of performing intra prediction, this circuit has the capability of performing the reference sample filter operation defined in the H.264 standard, and the smoothing and strong sample filter operations defined in the HEVC standard. We reduced the circuit size by sharing the circuit blocks for common operations and internal storage, and improved the circuit performance by parallel processing. The proposed circuit was described at RTL using Verilog HDL and its functionality was verified by using NC-Verilog of Cadence. The RTL circuit was synthesized by using Design Compiler of Synopsys and 130nm standard cell library. The synthesized gate-level circuit consists of 69,694 gates and processes 100 ~ 280 frames per second for 4K-UHD HEVC images at the maximum operation frequency of 157MHz.

• Journal of Korea Spatial Information System Society
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• v.10 no.4
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• pp.47-58
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• 2008

With the recent development of the ubiquitous computing technology, there are increasing interest and research in technologies such as sensors and RFID related to information recognition and location positioning in various ubiquitous fields. Especially, a standard specification was required for compatibility and interoperability in various RTLS(Real-Time Locating Systems) according to the development of RTLS to provide location and status information of moving objects using the RFID Tag. For these reasons, the ISO/IEC published the RTLS standard specification for compatibility and interoperability in RTLS. Therefore, in this paper, we designed and im plemented RTLS based on the spatial DSMS(Data Stream Management Stream) for efficiently managing and searching the incoming data stream of moving objects. The spatial DSMS is an extended system of STREAM(STanford stREam datA Manager) developed by Standford University to make various spatial operations possible. RTLS based on the spatial DSMS uses the SOAP(Simple Object Access Protocol) message between client and server for interoperability and translates client's SOAP message into CQL(Continuous Query Language) of the spatial DSMS. Finally, we proved the efficiency of RTLS based on the spatial DSMS by applying it for the staff location management service.

• Journal of Internet Computing and Services
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• v.10 no.6
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• pp.7-17
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• 2009

The development of wireless communication MAC layer is usually released as SoC which is a combination in hardware and software. In this system development environment, an environment for software development and verification is necessary because the hardware development takes a lot of time priori to completion. In integrated development of hardware and software, simulation environment of hardware and software provided by hardware modeling using HDL at RTL and ISS respectively. By increasing the development complexity of system, ESL design modeling systems at higher abstraction level than RTL has already prompted. The ESL design is divided untime model and time model. This paper present design and implementation of MCU for untime model simulation, not time model. Proposed MCU can optimize the system at early step of system development and move up the development completion time by verifying the system function easily and rapidly than part required exact time in untime model. In this paper, we present an MCU module based on SystemC and UC/OS-II Module providing real-time operate system.

• Journal of Internet Computing and Services
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• v.25 no.1
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• pp.29-37
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• 2024

In this paper, we propose an efficient image processing system to detect and track the movement of specific objects such as patients. The proposed system extracts the outline area of an object from a binarized difference image by applying a thinning algorithm that enables more precise detection compared to previous algorithms and is advantageous for mixed-mode design. The binarization and thinning steps, which require a lot of computation, are designed based on RTL (Register Transfer Level) and replaced with optimized hardware blocks through logic circuit synthesis. The designed binarization and thinning block was synthesized into a logic circuit using the standard 180n CMOS library and its operation was verified through simulation. To compare software-based performance, performance analysis of binary and thinning operations was also performed by applying sample images with 640 × 360 resolution in a 32-bit FPGA embedded system environment. As a result of verification, it was confirmed that the mixed-mode design can improve the processing speed by 93.8% in the binary and thinning stages compared to the previous software-only processing speed. The proposed mixed-mode system for object recognition is expected to be able to efficiently monitor patient movements even in an edge computing environment where artificial intelligence networks are not applied.

• Electronics and Telecommunications Trends
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• v.27 no.5
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• pp.36-43
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• 2012

본고에서는 멀티미디어 응용을 위한 멀티 코어 가상 플랫폼 설계 및 검증 방법에 대해서 기술한다. 최근에 멀티미디어 응용인 MPEG-4, H.264, HEVC(High Efficiency Video Coding), 3D 및 홀로그램과 같은 대용량 데이터를 처리하기 위해 다수 개의 코어로 구성된 멀티 코어 플랫폼을 사용한다. 기존의 RTL(Register Transfer Level) 기반의 멀티 코어 플랫폼에서 멀티미디어 응용을 설계하고 검증하는데 시뮬레이션 시간에 의한 제약 사항이 존재한다. 이를 해결하기 위해 시스템 수준에서 하드웨어의 SW 모델로 구성된 가상 플랫폼을 사용한다. 가상 플랫폼은 기존의 RTL 플랫폼보다 100~200배 빠른 고속 시뮬레이션이 가능하므로 멀티미디어 응용에 따른 성능 분석 및 구조 탐색을 통해서 시스템 성능을 향상 시킬 수 있다. 본고에서는 8~32개 멀티 코어 가상 플랫폼에 H.264 디코더를 적용하여 성능 분석하는 방법과 실험 결과에 대해서 기술한다.