• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.4
• /
• pp.866-872
• /
• 2004

In fingerprint verification and identification, fingerprint and background region should be segmented. For this purpose, most systems obtain variance of brightness of X and Y direction using Sobel mask. To decide given local region is background or not, the variance is compared with a certain threshold. Although this method is simple, most fingerprint image does not separated with two region of fingerprint and background region. In this paper, we presented a new segmentation algorithm based on run-length connectivity analysis. For a given binary image after thresholding, suggested algorithm calculates RL of X and Y direction. Until the given image is segmented to two regions, small run region is successively inverted. Experimental result show that this algorithm effectively separates fingerprint region and background region.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.54 no.8
• /
• pp.475-481
• /
• 2005

In the existing ICT technique, the mounted electronic devices on the printed circuit board are tested whether the devices are good or not by comparing and measuring the value of the devices after separating the devices to be tested from around it based on the guarding method. But, in case that resistance, inductor and capacitor are configured as a parallel circuit on the circuit pattern, values for each device can not be measured because the total impedance value of the parallel circuit is measured. Accordingly, it is impossible to test whether the parallel circuit is good or not in case that the measured impedance value is within the tolerance error. Also, it is difficult to identify that which device among R, L and C of the parallel circuit is bad in case that the measured impedance value is out of the tolerance error. Accordingly, this paper proposes a test method which can enhance the quality and productivity by separating and measuring accurately R, L and C components from the RLC parallel circuits on the device-mounted printed circuit board. First, the RLC parallel circuit to be test is separated electrically from around it using three-terminal guarding technique. And then R, L and C values are computed based on the total impedance values and phase angles between voltage and current of the parallel circuit measured from two AC input signals with other frequency, Finally, the availability and accuracy of the proposed test method is verified by reviewing the simulation results.

• Proceedings of the IEEK Conference
• /
• 2004.06b
• /
• pp.435-438
• /
• 2004

This paper presents a new analytical model to suppress RLC resonance effects in power/ground lines due to a decoupling capacitor. First, the resonance frequency of an RLC circuit which is composed of package inductance. decoupling capacitor, and output drivers is accurately estimated. Next, using the estimated resonance frequency, a suitable decoupling capacitor sire is determined. Then, a novel design methodology to suppress the resonance effects is developed. Finally, its validity is shown by using $0.18 {\mu}m$ process-based-HSPICE simulation.

• Proceedings of the KIPE Conference
• /
• 2006.06a
• /
• pp.235-238
• /
• 2006

As the screen size of LCD TV increases, an external electrode fluorescent lamp (EEFL) has been suggested to be applicable as backlight source for LCD TV. Since the EEFL has non-linear characteristics, which makes the analysis and design complicated. In this paper, the characteristics of the EEFL are investigated and a full-bridge RLC series-resonant inverter is analyzed and designed for EEFL backlight of 32-inch LCD TV. Finally, the experimental results are shown to validate the analysis and design.

• Proceedings of the KIEE Conference
• /
• 2002.04a
• /
• pp.183-185
• /
• 2002

This paper proposes the test method for the testing of a RLC parallel circuit on the electronic circuit board. This method utilizes a guarding circuit and a phase detection circuit. The guarding circuit separates electrically the tested device or circuit from printed circuit board. Phase detector estimates the phase difference from two signals, voltage and current. This method computes R. L and C value from phase difference($\theta$) and impedance value(Z) obtained by enforcing two other frequence stimulus under the guarding state.

• 제어로봇시스템학회:학술대회논문집
• /
• 2000.10a
• /
• pp.526-526
• /
• 2000

The present has a double objective. The first one is to compare and estimate sixteen continuous-time methods through the identificatiun of a system consisted with an RLC electrical circuit. These sixteen methods are classified into three groups that are the linear filters, the modulating functions and the integral methods. The second objective is to estimate directly the physical parameters of the RLC circuit, without resorting to a discrete-time model. The system is consisted of a coil with inductance L and resistance H, and of a capacitor with capacitance C. Having written the physical equations which describe the behavior of the system, the transfer function in where the initial conditions appear is given. These initial conditions should be taken into account during the parameter estimation phase, because they are inevitable within the framework of real signals. A physical interpretation of the identified models is tempted by the direct estimation of the physical parameters L and C. In conclusion, a classification of the studied methods is proposed.

• 제어로봇시스템학회:학술대회논문집
• /
• 2001.10a
• /
• pp.107.6-107
• /
• 2001

Genetic alogorithm(GA) is a well-known global optimization algorithm. However, as the searching bounds grow wider., performance of local optimization deteriorates. In this paper, we propose a hybrid algorithm which integrates the gradient algorithm and GA so as to reinforce the performance of local optimization. We apply this algorithm to the system identification of second order RLC circuit. Identification results show that the proposed algorithm gets the better and robust performance to find the exact values of RLC elements.

• IE interfaces
• /
• v.11 no.2
• /
• pp.79-92
• /
• 1998

For the PCB inspection by computer vision, in some cases, the MRLC file should prepared. The MRLC file contains a RLC(Run Length Code) and a direction flag. In this paper, a generating method of MRLC is described. It is composed of two procedure as followings; (i) rasterizing Gerber file which is a vectorized image of PCB panel, and (ii) calculating a MRLC that is useful for the inspection as a template image. The suggested procedures are written in C-language and executable on Windows 95 and Windows NT.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.5
• /
• pp.13-26
• /
• 1999

This paper presents a metric that can guide to optimal circuit models for interconnects among various models, given interconnect parameters and operating environment. To get this goal, we categorize interconnects into RC~c1ass and RLC-c1ass model domains based on the quantitative modeling error analysis using total resistance, inductance and capacitance of interconnects as well as operating frequency. RC~c1ass circuit models, which include most on~chip interconnects, can be efficiently analyzed by using the model~order reduction techniques. RLC-c1ass circuit models are constructed using one of three candidates, ILC(Iterative Ladder Circuit) macromodels, MC(Method of Characteristics) macromodels, and state-based convolution method, the selection process of which is based upon the allowable modeling error and electrical parameters of interconnects. We propose the model domain diagram leading to optimal circuit models and the division of model domains has been achieved considering the simulation cost of macromodels under the environmental assumption of the general purpose circuit simulator such as SPICE. The macromodeling method presented in this paper keeps the passivity of the original interconnects and accordingly guarantees the unconditional stability of circuit models.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.7 no.1
• /
• pp.142-148
• /
• 2003

We compress medical images in order to solve problems both of request of storage mediums and of a low network speed. In this paper, integration compression environment has been developed for unity of various compression methods. Various compression methods that are implemented by integration compression environment, RLC, Lossless JPEG, and JPEG, comply with the DICOM 3.0. A compression method using DWT is implemented at it. And a unit method of Lossless compression method and lossy compression method is designed to improve images quality and to progress compression ratio. Diverse medical images can be compressed by each compression method. And integration compression environment is operated together database so that information of medical images is administered.