• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.31-43
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• 1999

The main goal of this paper is to design a high performance SVP(Stack based Video Processor) for network applications. The SVP is a comprehensive scheme; 'better' in the sense that it is an optimal selection of previously proposed enhancements of a stack machine and a video processor. This can process effectively object-based video data using a S-RISC(Stack-based Reduced Instruction Set Computer) with a semi -general-purpose architecture having a stack buffer for OOP(Object-Oriented Programming) with many small procedures at running programs. And it includes a vector processor that can improve the MPEG coding speed. The vector processor in the SVP can execute advanced mode motion compensation, motion prediction by half pixel and SA-DCT(Shape Adaptive-Discrete Cosine Transform) of MPEG-4. Absolutors and halfers in the vector processor make this architecture extensive to a encoder. We also designed a VLSI stack-oriented video processor using the proposed architecture of stack-oriented video decoding. It was designed with O.5$\mu\textrm{m}$ 3LM standard-cell technology, and has 110K logic gates and 12 Kbits SRAM internal buffer. The operating frequency is 50MHz. This executes algorithms of video decoding for QCIF 15fps(frame per second), maximum rate of VLBV(Very Low Bitrate Video) in MPEG-4.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.1011-1012
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• 2006

In this paper, implementation process of standard platform for T-DMB Receiver in low-cost and small-size are following: First, implement SoC for 32 bit RISC CPU and 16 bit DSP, Hardware H.264 CODEC, Post Processor or Video Display, Audio Processor, I/O Device. Second, implement Real Time OS for flexible application. Third, propose simple architecture for interface with peripheral devices using one-chip processor.

• Journal of the Korea Society of Computer and Information
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• v.14 no.11
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• pp.97-103
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• 2009

In this thesis, we discuss the implementation of parallel processing system which is able to get a high degree of efficiency(size, cost, performance and flexibility) by using $Nios^{(R)}$ II(32bit RISC(Reduced Instruction Set Computer) processor) embedded processor in DE2-$70^{(R)}$ reference board. The designed Parallel processing system is master-slave, shared memory and MIMD(Mu1tiple Instruction-Multiple Data stream) architecture with 4-processor. For performance test of system, N-point FFT is used. The result is represented speed-up as follow; in the case of using 2-processor(core), speed-up is shown as average 1.8 times as 1-processor's. When 4-processor, the speed-up is shown as average 2.4 times as it's.

• ETRI Journal
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• v.10 no.3
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• pp.24-35
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• 1988

본 논문은 한국전자통신연구소에서 개발하고 있는 RISC 형태의 32비트 프로세서인 HARP(High-performance Architecture for Risc-type Processor)의 파이프라인 설계와 익셉션 처리 방법에 관한 것이다. HARP의 파이프라인은 명렁어 페치의 병목현상을 해결하기 위하여 중첩된 메모리 액세스 방법을 사용하며 이는 5단계로 구성된다. 그리고 명령어 동시 수행으로 인해 발생하는 자원 충돌을 해결하기 위하여 bypassing logic, instruction fetch unit 및 code-reorganizer를 사용한다. 명령어 수행시 파이프라인 상에서 발생하는 익셉션에 대해서는 익셉션 처리의 복잡성을 피하기 위하여 instruction restart 방법을 사용한다.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.755-758
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• 1998

As the performance of microprocessor improves, the design complexity grows exponentially. Therefor, it is very important to make the bug-free model as early as possible in a design life-cycle. This paper describes the simulation-based functional verification methodology for the RTL level description model. It is performed by multi-stage verification methods using extensive hand-generated self-checking tests supplemented with random tests. This approach is opplied to the functional verification of the GPU processor of Raptor and various bugs are detected.

• Proceedings of the Korea Multimedia Society Conference
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• 2002.11b
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• pp.609-612
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• 2002

본 논문은 다양한 멀티미디어 응용을 위한 재구성가능(reconfigurable) 구조의 프로세서 설계에 대해서 연구하였다. 설계된 프로세서는 RISC 코어 프로세서와 코스-그레인(coarse-grain) 구조의 재구성가능 셀들의 배열로 이루어진 처리 유닛으로 구성되었다. 여기서 사용된 RISC 코어 프로세서는 하드웨어 구조를 간단히 하기 위하여 MIPS 명령어들 중에서 사용빈도가 높은 것들만 고려하였으며, 재구성가능 처리를 위한 별도의 명령어를 추가하였다. 본 논문에서 제시한 재구성가능 프로세서는 VHDL로 모델링하여 실행을 검증하였으며, 하드웨어의 유연성을 증가하여 다양한 멀티미디어 응용에 적용함과 아울러 속도향상에 기여함을 볼 수 있었다.

• Journal of information and communication convergence engineering
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• v.6 no.4
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• pp.376-382
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• 2008

Developing highly cost-efficient and reliable embedded systems demands hardware/software co-design and co-simulation due to fast TTM and verification issues. So, it is essential that Platform-Based SoC design methodology be used for enhanced reusability. This paper addresses a reusable SoC platform based on OpenCores soft processor with reconfigurable architectures for hardware/software codesign methodology. The platform includes a OpenRISC microprocessor, some basic peripherals and WISHBONE bus and it uses the set of development environment including compiler, assembler, and debugger. The platform is very flexible due to easy configuration through a system configuration file and is reliable because all designed SoC and IPs are verified in the various test environments. Also the platform is prototyped using the Xilinx Spartan3 FPGA development board and is implemented to a single chip using the Magnachip cell library based on $0.18{\mu}m$ 1-poly 6-metal technology.

• Proceedings of the Korea Information Processing Society Conference
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• 2021.11a
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• pp.217-220
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• 2021

ICISC'19에서 기존 CHAM과 동일한 구조와 규격을 갖지만, 라운드 수만 증가시킨 revised CHAM이 발표되었다. CHAM은 사물인터넷에서 사용되는 저사양 프로세서에서 효율적인 구현이 가능한 특징을 갖고 있다. AVR, ARM 프로세서 상에서의 CHAM 암호 알고리즘에 대한 최적 구현은 존재하지만, 아직 RISC-V 프로세서 상에서의 CHAM 구현은 존재하지 않는다. 따라서, 본 논문에서는 RISC-V 프로세서 상에서의 Revised CHAM 알고리즘을 최초로 구현을 제안한다. CHAM 라운드 함수의 내부 구조의 일부를 생략하여 최적 구현하였다. 그리고 홀수 라운드와 짝수 라운드를 모듈별로 구현하여 필요에 따라 모듈을 호출하여 손쉽게 사용할 수 있게 하였다. 결과적으로, RISC-V 상에서 제안 기법 적용하기 전보다 제안 기법 적용 후에 12%의 속도 향상을 달성하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1211-1217
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• 2005

Current generation embedded systems are built around only a small number of SOCs, which are again based on general-purpose embedded micro-processors, such as ARM and MIPS. These RISC-based processors are not, however, designed for specific functions such as networking and multimedia processing, whose importances have increased dramatically in recent years. Network devices for small business and home networks, are especially dependent upon such SOCs based on general processors. Except for PHY and MAC layer functions, which are built with hardware, all the network functions are processed by the embedded micro-processor. Enabling technologies such as VDSL and FTTH promise Internet access with a much higher speed, while at the same time explore the limitations of general purpose microprocessors. In this paper we design a network processor, embed it into an SOC for Home gateway, evaluate the performance rigorously, and gauge a possibility for commercialization.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.313-316
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• 2002

This paper presents the design and implementation of a crypto processor, a special-purpose microprocessor optimized for the execution of cryptography algorithms. This crypto processor can be used fur various security applications such as storage devices, embedded systems, network routers, etc. The crypto processor consists of a 32-bit RISC processor block and a coprocessor block dedicated to the SEED and triple-DES (data encryption standard) symmetric key crypto (cryptography) algorithms. The crypto processor has been designed and fabricated as a single VLSI chip using 0.5 $\mu\textrm{m}$ CMOS technology. To test and demonstrate the capabilities of this chip, a custom board providing real-time data security for a data storage device has been developed. Testing results show that the crypto processor operates correctly at a working frequency of 30MHz and a bandwidth o1240Mbps.