• Proceedings of the Korea Society for Simulation Conference
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• 2002.11a
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• pp.73-77
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• 2002

이 논문은 빠른 ASIP(application specific instruction processor) 시뮬레이션을 위한 재적응성을 가진 컴파일드 시뮬레이션 기법에 대해 이야기 한다. 다양한 응용분야에서의 설계 요구사항을 충족시키는 ASIP의 빠른 개발을 위해서, 건전한 설계 방법론 및 고성능의 시뮬레이터가 필요하다. 본 논문에서는 HiX$R^2$라는 ADL(architecture description language)을 이용하여 인스트럭션 수준에서 컴파일드 시뮬레이터를 자동 생성하였다. 컴파일드 시뮬레이션은 시뮬레이션 수행 시 반복되는 인스트럭션 페칭 및 디코딩 부분을 시뮬레이션 런-타임 이전에 미리 수행함으로서 일반적으로 사용되는 인터프리티브 시뮬레이션에 비하여 큰 성능향상을 얻을 수 있다. HiX$R^2$에 기반 한 컴파일드 시뮬레이션은 ARM9 프로세서와 CalmRISC32 프로세서 예제들로 수행하였고, 결과로서 인터프리티브 방식에 비해 150배 이상의 성능향상이 있었다.

• Proceedings of the Korea Society for Simulation Conference
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• 2003.06a
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• pp.79-84
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• 2003

이 논문은 빠른 ASIP(application specific instruction processor) 평가를 위한 재적응성을 가진 컴파일러/시뮬레이터 환경에 대해 이야기한다. ASIP의 성능은 하드웨어 구조뿐만 아니라, 수행되는 응용 소프트웨어에 영향을 받기 때문에, 높은 성능의 ASIP 개발을 위해서는 컴파일러 및 시뮬레이터의 개발이 선행되어야 한다. 그러나 다양한 ASIP 구조에 따라 적합한 고성능의 컴파일러/시뮬레이터를 만드는 일은 매우 시간 소모적인 일이 될 뿐만 아니라, 오류가 발생하기도 쉽다. 본 논문에서는 HiXR2라는 ADL(architecture description language)을 이용하여 명령어 구조를 기술하고 이를 바탕으로 컴파일러와 시뮬레이터를 자동 생성하였다. HiXR2의 재적응성 및 생성된 컴파일러/시뮬레이터의 정확성을 검증하기 위하여 ARM9 프로세서와 CalmRISC32 프로세서 구조를 각각 기술하고, 각각에 대하여 응용프로그램 코드를 컴파일 및 시뮬레이션 하는 예제를 보였다.

• Journal of the Korea Society for Simulation
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• v.12 no.2
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• pp.45-53
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• 2003

This paper presents a retargetable compiled assembly simulation technique for fast ASIP(application specific instruction processor) simulation. Development of ASIP which satisfies design requirements in various fields of applications such as telecommunication, wireless network, etc. needs formal design methodology and high-performance relevant software environments such as compiler and simulator In this paper, we employ the architecture description language(ADL) named ${HiXR}^2$ to automatically synthesize an instruction-level compiled assembly simulator. A compiled simulation has benefit of time efficiency to interpretive one because it performs instruction fetching and decoding at compile time. Especially, in case of assembly simulation, instruction decoding is usually a time-consuming job(string operation), so the compiled simulation of assembly simulation is more efficient than that of binary simulation. Performance improvement of the compiled assembly simulation based on ${HiXR}^2$ is exemplified with an ARM9 architecture and a CalmRISC32 architecture. As a result, the compiled simulation is about 150 times faster than interpretive one.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1545-1552
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• 2013

This paper presents an implementation of embedded platform based ARM A8-cortex processor for android supporting. The development board for S5PV210 is a platform that is suitable for code development of SAMSUNG's S5PV210 32bit RICS micro controller(ARMv7) architecture for hand-held device and general applications. Embedded platform development board offers various function and high efficiencies. In addition to the high performance, the embedded platform offers low current consumption, ensuring low costs and power.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.959-961
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• 2003

In this paper, we describe implemented DMAC (Direct Memory Access Controller) architecture on Altera's $Excalibur^{TM}$ that includes industry-standard $ARM922T^{TM}$ 32-bit RISC processor core operating at 200 MHz. We implemented DMAC based on AMBA (Advanced Micro-controller Bus Architecture) AHB (Advanced Micro-performance Bus) interface. Implemented DMAC has 8-channel and can extend supportable channel count according to user application. We used round-robin method for priority selection. Implemented DMAC supports data transfer between Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory. The max transfer count is 1024 per a time and it can support byte, half-word and word transfer according to AHB protocol (HSIZE signals). We implemented with VHDL and functional verification using $ModelSim^{TM}$. Then, we synthesized using $LeonardoSpectrum^{TM}$ with Altera $Excalibur^{TM}$ library. We did FPGA P&R and targeting using $Quartus^{TM}$. We can use implemented DMAC module at any system that needs high speed and broad bandwidth data transfers.

• Proceedings of the Korea Information Processing Society Conference
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• 2021.05a
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• pp.121-124
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• 2021

사물 인터넷 기술의 발전에 따라 생활 곳곳에서 여러 가지 임베디드 기기들을 찾아볼 수 있게 되었다. 하지만 임베디드 기기의 보급이 늘어감에 따라 이러한 임베디드 기기를 노린 공격도 함께 늘어가고 있다. 이에 따라 임베디드 기기의 보안에 대한 다양한 연구들이 진행되고 있는데 본 연구에서는 대다수의 임베디드 기기에 적용된 RISC 아키텍처 기반 보안 기술에 대하여 살펴보고 향후 발전 방향에 대해 살펴보도록 하겠다.

• Proceedings of the Korean Society of Computer Information Conference
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• 2022.07a
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• pp.263-266
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• 2022

최근 프로세서 제조공정의 급속한 발전으로 프로세서의 종류에 상관없이 같은 운영체제를 설치 할 수 있게 되었다. 하지만 근본적으로 프로세서의 종류에 따라 차이점이 있고, 동작방식이 다르기 때문에 포렌식 할 경우 같은 운영체제라도 다른 결과가 나올 수 있다. 본 논문은 디지털포렌식을 이용하여 CISC 프로세서의 Windows 운영체제와 RISC 프로세서의 Windows운영체제를 비교하고, 프로세서 방식에 따른 차이점을 통해 후속 연구 방향을 제시한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.435-438
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• 2003

The MS card data transfer system using blue-tooth protocol ran communicate the MS card data wirelessly and does not take an extra communication expense which is a weakness point of existing wireless communication system. This Blue-tooth system, which has excellent security and no extra communication expense, can efficiently communicate data of the place ,where can be solved with small scale wireless network, such as the theme-park or gasoline-station. Existing wireless communication system compose network using wireless-LAN protocol which has extra communication expense, or with RF protocol which has poor security. But this system suitable for LAN because it has not extra communication expense and it has excellent security cause frequency-hopping of Blue-tooth protocol. The MS card data transfer system using blue-tooth protocol has low power, high performance RISC processor and large scale 16-gray graphic LCD which is suitable for portable unit. The MS card data transfer system can efficiently control depot for a long time because it has low power, excellent security and no extra communication expense.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.4
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• pp.214-221
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• 2003

This paper shows an implementation of video codec (coder/decoder) on an embedded system. The video codec supports both H.261 and H.263 standards. For efficient real-time processing, the video codec is partitioned into a software module and a hardware module. Both modules are codesigned on an embedded system. The software module is processed on a real-time operating system and a RISC processor. It cooperates with the hardware module to compress and decompress images in real time. AMBA (Advanced Microcontroller Bus Architecture) AHB (Advanced High-performance Bus) is used as the system bus. The hardware module works both as AHB masters and as AHB slaves. The encoder part of the hardware module operates in a pipelines mode to compress images in real time. The video codec compresses 15 CIF frames and simultaneously decompresses 15 CIF frames in a second according to H.261 or H.263 standard at 33 MHz frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.3029-3034
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• 2014

The paper describes the scleral diagnostic system implementation for human eyes by using the scleral color code and vessels sign pattern code generations. The system is based on the high performance DSP image signal processor, programmable gain control for preprocessing and RISC SD frames storage. RGB image signals are optimized by PGC, the edge image is detected form the gray image converted. The processing algorithms are executed by scleral color code generation and scleral vessels sign pattern code creation for discriminating and matching. The scleral symptomatic color code is generated by YCbCr values at memory map tolerated and the vessel sign pattern code is created by digitizing the 24 clock and 13 ring zones, overlay matching and tolerances. The experimental results for performance are that the system runs 40ms, and the color and pattern for diagnostic errors are around 20% and 24% on average. The system and technique enable a scleral diagnosis with subdividing the patterns and patient database.