• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2164-2170
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• 2010

Digital Radio Frequency Memory, ( as DRFM ), is a device with the ability to restore output to the input RF signal in the required time after storing the incoming RF signals. Therefore DRFM is widely used in Jammer, EW Simulator, Target Echo Generator, and so on. This paper proposes its hardware implementation composed with the high frequency part and the digital processing part consisting of RF input/output module and local oscillator module. It is also proposed the replicated signal generation method which is consisted of the Analog-Digital conversion in the form of pulsed RF signal quantization, and FPGA to save and produce the playback signal, and RF signals to produce a Digital-Analog Conversion in the digital processing unit. This proposed scheme applied to test board and confirmed the validity of the proposed scheme through the test results obtained by the simulated input signals.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.339-342
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• 2005

In order to support ultrawide-band signal generation for low rate WPAN, several types of signal generation mechanisms are suggested such as Chaos, Impluse, and Chirp signals by the activity of IEEE 802.15.4a. The communication system applied chaos theory may have ultrawide-band characteristics with spread spectrum and immunity from multipath effect. In order to use the advantage of chaotic signal generation, we introduce the system implementation of communication and networking systems with the chaos UWB signal. This system may be composed of mainly three parts in hardware architecture : RF transmission with chaotic signal generation, signal receiver using amplifiers and filters, and 8051 & FPGA unit. The most difficult part is to implement the chaotic signal generator and build transceiver with it. The implementation of the system is devidced into two parts i.e. RF blocks and digital blocks with amplifiers, filters, ADC, 8051 processor, and FPGA. In this paper, we introduce the system block diagram for chaotic communications. Mainly the RF block is important for the system to have good performance based on the chaotic signal generator. And the main control board functions for controlling RF blocks, processing Tx and Rx data, and networking in MAC layer.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.2 no.1
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• pp.37-49
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• 2008

At the present time the task of designing a highly integrated ZigBee radio frequency (RF) receiver with an excellent coexistence performance is still very demanding and challenging. This paper presents a number of system issues and design considerations for a ZigBee RF receiver, namely IEEE 802.15.4, for coexistence with wireless devices in the 2.4-GHz ISM-band. With regard to IEEE 802.15.4, the paper analyzes receiver performance requirements for; system noise figure (NF), system third-order intercept point (system-IIP3), local oscillator phase noise and selectivity. Based on some assumptions, the paper illustrates the relationship between minimum detectable signal (MDS) and various situations that involve the effects of electromagnetic interference generated by other wireless devices. We infer the necessity of much more stringent specification requirements than the published standard for various wireless communication field environments

• ETRI Journal
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• v.36 no.3
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• pp.352-360
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• 2014

This paper presents a 900 MHz zero-IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ${\Delta}{\Sigma}$ fractional-N frequency synthesizer. In the RF front end, re-use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current-driven passive mixer in Rx and voltage-mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty-cycle in local oscillator clocks. The overall Rx-baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a $0.18{\mu}$ CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of -2 dBm, a sensitivity level of -103 dBm at 100 Kbps with PER < 1%, an Rx input $P_{1dB}$ of -11 dBm, and an Rx input IP3 of -2.3 dBm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.638-646
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• 2005

In recent wireless communications, direct conversion transceiver or If sampling SDR-based receivers have being designed as an alternative to conventional transceiver topologies. In direct conversion receiver a.chitectu.e, the 1.equency/phase offset between the RF input signal and the local oscillator signal is a major impairment factor even though the conventional AFC/APC compensates the service deterioration due to the offset. To rover the limited tracking range of the conventional method and effectively aid compensation scheme in terms of I/Q channel imbalances, the frequency/phase offset compensation in RF-front end signal stage is proposed in this paper. In RF-front end, the varying phase offset besides the fixed large frequency/phase offset are corrected by using early-late phase compensator. A more simple frequency and phase tacking function in digital signal processing stage of direct conversion receiver is effectively available by an ingenious frequency/phase offset tracking method in RF front-end stage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.7 s.110
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• pp.659-664
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• 2006

This paper reports a high power 60 GHz push-push oscillator fabricated using $0.12{\mu}m$ metamorphic high electron-mobility transistors(mHEMTs). The devices with a $0.12{\mu}m$ gate-length exhibited good DC and RF characteristics such as a maximum drain current of 700 mA/mm, a peak gm of 660 mS/mm, an $f_T$ of 170 GHz, and an $f_{MAX}$ of more than 300 GHz. By combining two sub-oscillators having $6{\times}50{\mu}m$ periphery mHEMT, the push-push oscillator achieved a 6.3 dBm of output power at 59.5 GHz with more than - 35 dBc fundamental suppression. The phase noise of - 81.5 dBc/Hz at 1 MHz offset was measured. This is one of the highest output power obtained using mHEMT technology without buffer amplifier, and demonstrates the potential of mHEMT technology for cost effective millimeter-wave commercial applications.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.81-84
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• 2000

This paper has been studied the design of 16-QAM demodulator used in broadband wireless local loop subscriber station. In B-WLL systems, transmission signal experience the inter symbol interference(ISI) due to multipath, frequency offset of RF/IF local oscillator and phase offset. In this paper, we discuss the effective data recovery algorithm for 16-QAM demodulator to compensate the distorted signal from ISI, frequency offset and phase offset.

• Bulletin of the Korean Space Science Society
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• 2003.10a
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• pp.107-107
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• 2003

GPS Receiver는 위성에 위치 정보와 시간 정보등을 제공하고 navigation을 관리하며 이에 관련된 signal을 processing하는 역할을 한다. 2005년에 발사 예정인 KOMPSAT-2 위성에는 Alcatel에서 제작된 Topstar 3000이 사용된다. Topstar 3000은 RF 부분과 digital 처리부분으로 구성된 GPS core부분과 MLD-STD_1553, DC-DC converter, 그리고 Ovened-controlled Oscillator(OCXO)부분으로 구성되는 option module 부분으로 구성되어 있다. 본 논문에서는 GPS Signal Simulator로 KOMPSAT-2의 실제 궤도를 구현해서 Sun-Point Mode와 Earth-Point Mode 등 여러가지 Mode 에서 GPS Receiver의 시간, 위치, 속도 정보의 정확성에 대한 성능이 분석된다.

• Journal of electromagnetic engineering and science
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• v.10 no.1
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• pp.35-38
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• 2010

A fully integrated parallel-coupled 6-GHz quadrature voltage-controlled oscillator (QVCO) has been designed. The symmetrical parallel-coupled quadrature VCO is implemented using 0.13-${\mu}m$ CMOS process. The measured phase noise is -101.05 dBc/Hz at an offset frequency of 1 MHz. The tuning range of 710 MHz is achieved with a control voltage ranging from 0.3 to 1.4 V. The average output phase error is about $1.26^{\circ}$ including cables and connectors. The QVCO dissipates 10 mA including buffer from the 1.5 V supply voltage. The output characteristic of the differential injection-locked frequency divider (DILFD), which has similar topology to the QVCO, is presented.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.190-197
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• 2011

This paper presents a 144 GHz divide-by-2 injection locked frequency divider (ILFD) with inductive feedback developed in a commercial 90-nm Si RFCMOS technology. It was demonstrated that division-by-2 operation is achieved with input power down to -12 dBm, with measured locking range of 0.96 GHz (144.18 - 145.14 GHz) at input power of -3 dBm. To the authors' best knowledge, this is the highest operation frequency for ILFD based on a 90-nm CMOS technology. From supply voltage of 1.8 V, the circuit draws 5.7 mA including both core and buffer. The fabricated chip occupies 0.54 mm ${\times}$ 0.69 mm including the DC and RF pads.