• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.148-156
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• 2001

This paper proposed embedded application-specific microprocessor(YS-RDSP) whose structure has an additional DSP processor on chip. The YS-RDSP can execute maximum four instructions in parallel. To make program size shorter, 16-bit and 32-bit instruction lengths are supported in YS-RDSP. The YS-RDSP provides programmability. controllability, DSP processing ability, and includes eight-kilobyte on-chip ROM and eight-kilobyte RAM. System controller on the chip gives three power-down modes for low-power operation, and SLEEP instruction changes operation statue of CPU core and peripherals. YS-RDSP processor was implemented with Verilog HDL on top-down methodology, and it was improved and verified by cycle-based simulator written in C-language. The verified model was synthesized with 0.7um, 3.3V CMOS standard cell library, and the layout size was 10.7mm78.4mm which was implemented by using automatic P&R software.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.403-404
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• 2013

최근 scaling down의 한계에 부딪힌 DRAM과 Flash Memory를 대체하기 위한 차세대 메모리(Next Generation Memory)에 대한 연구가 활발히 진행되고 있다. ITRS (international technology roadmap for semiconductors)에 따르면 PRAM (phase change RAM), RRAM (resistive RAM), STT-MRAM (spin transfer torque magnetic RAM) 등이 차세대 메모리로써 부상하고 있다. 그 중 RRAM은 간단한 구조로 인한 고집적화, 빠른 program/erase 속도 (100~10 ns), 낮은 동작 전압 등의 장점을 갖고 있어 다른 차세대 메모리 중에서도 높은 평가를 받고 있다 [1]. 현재 RRAM은 주로 금속-산화물계(Metal-Oxide) 저항 변화 물질을 기반으로 연구가 활발하게 진행되고 있다. 하지만 근본적으로 공정 과정에서 산소에 의한 오염으로 인해 수율이 낮은 문제를 갖고 있으며, Endurance 및 Retention 등의 신뢰성이 떨어지는 단점이 있다. 따라서, 본 연구진은 산소 오염에 의한 신뢰성 문제를 근본적으로 해결할 수 있는 다양한 금속-질화물(Metal-Nitride) 기반의 저항 변화 물질을 제안해 연구를 진행하고 있으며, 우수한 열적 안정성($>450^{\circ}C$, 높은 종횡비, Cu 확산 방지 역할, 높은 공정 호환성 [2] 등의 장점을 가진 WN 박막을 저항 변화 물질로 사용하여 저항 변화 메모리를 구현하기 위한 연구를 진행하였다. WN 박막은 RF magnetron sputtering 방법을 사용하여 Ar/$N_2$ 가스를 20/30 sccm, 동작 압력 20 mTorr 조건에서 120 nm 의 두께로 증착하였고, E-beam Evaporation 방법을 통하여 Ti 상부 전극을 100 nm 증착하였다. I-V 실험결과, WN 기반의 RRAM은 양전압에서 SET 동작이 일어나며, 음전압에서 RESET 동작을 하는 bipolar 스위칭 특성을 보였으며, 읽기 전압 0.1 V에서 ~1 order의 저항비를 확보하였다. 신뢰성 분석 결과, $10^3$번의 Endurance 특성 및 $10^5$초의 긴 Retention time을 확보할 수 있었다. 또한, 고저항 상태에서는 Space-charge-limited Conduction, 저저항 상태에서는 Ohmic Conduction의 전도 특성을 보임에 따라 저항 변화 메카니즘이 filamentary conduction model로 확인되었다 [3]. 본 연구에서 개발한 WN 기반의 RRAM은 우수한 저항 변화 특성과 함께 높은 재료적 안정성, 그리고 기존 반도체 공정 호환성이 매우 높은 강점을 갖고 있어 핵심적인 차세대 메모리가 될 것으로 기대된다.

• Journal of Embryo Transfer
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• v.28 no.4
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• pp.325-335
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• 2013

The study was set for one year to measure the effects of concentrate supplementation on reproductive performances and semen quality in indigenous rams. The study was conducted at the Department of Surgery and Obstetrics, Faculty of Veterinary Science, Bangladesh Agricultural University, Mymensingh, Bangladesh during the period from May 2011 to April 2012. Forteen ram lambs (4~5 months) were randomly divided into two equal groups (n=7); supplemented vs control. The animals of control group were maintained on natural grazing. Along with natural grazing the supplemented group was on supplemented feeding. The concentrate supplementation (Wheat bran, Crushed maize, Soy bean meal, Fish meal, DCP powder, Vitamin mineral premix, Salt) was provided @ 300 g/head /day to the supplemented group. Body weight, scrotal circumference, BCS and libido index were measured weekly. Age, body weight and scrotal circumference at puberty were recorded. Semen was collected once in a weak using artificial vagina and chilled at $5^{\circ}C$ for 48h for evaluation. Concentrate supplementation did not influence (p>0.05) body condition score, age, weight, scrotal circumference at puberty and libido index. Final body weight (kg), growth rate (g/d), scrotal circumference (cm) and scrotal growth rate (mm/15d) were significantly (p<0.05) higher in supplemented group of rams compared to control. Volume, concentration, motility and membrane potentiality of spermatozoa were varied significantly (p<0.05) in supplemented and control groups. However, density, mass motility, viability and sperm with normal acrosome, midpiece and tail were not differed insignificantly (p>0.05) in different observation times. It was concluded that concentrate supplementation with free grazing improved weight and scrotal circumference gain and semen production with increased quality in indigenous ram.

• Asian-Australasian Journal of Animal Sciences
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• v.27 no.5
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• pp.726-732
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• 2014

The objective of this study was to investigate the effect of maintenance system as well as the effect of Se, Zn, and vitamin E supplementation of ram-lambs on the slaughter value and concentration of mineral elements in the loin muscle of lambs. The experiment was conducted on 72 Polish Merino ram-lambs divided into three groups: group C, indoor with no supplement, 19 lambs; S, indoor with supplement, 23 lambs; G, outdoor with no supplement, 30 lambs. From birth all the lambs were maintained indoor with their dams and then weaned at the age of 8 weeks. The rams from group C and S were placed in individual straw-bedded pens and fattened individually with concentrate mixture offered ad libitum until the age of 16 weeks. The lambs from group G were grazed every day from May to July (2 months). During the fattening period each lamb from the supplemented group S was administered per os 1 mL 0.1% $Na_2SeO_4$ (Se, 0.42 mg), 3 mL 10% $ZnSO_4$ (Zn, 68 mg), and 1 mL premix protect vitamin E (0.1 g ${\alpha}$-tocopherol, 5 mg lysine, 5 mg methionine) daily. A comparison of half carcasses across the groups has shown no difference between the control group and the one with supplements, while the weight of half carcasses in the grazing group was smaller in comparison with groups C and S (p<0.001). The meat content in the pelvic limb showed no differences across all groups under study. The pelvic limb of grazing lambs contained less fat compared to the control and supplemented groups (p<0.001). The concentrations of Se and Zn in the blood plasma of ram-lambs from the supplemented group were significantly higher than for the control and grazing lambs. Inorganic Se and Zn supplementation with vitamin E to the diet of lambs increased Se and Zn levels in loin muscle (p<0.001) to $0.46{\mu}g/g$ and $32.9{\mu}g/g$ in fresh tissue, respectively.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1207-1210
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• 1998

차세대 DVD system의 audio 규격인 Dolby AC-3를 구현하는 방법으로 DSP 프로세서인 TMSC80을 사용하여 실시간 처리 가능한 하드웨어 바탕의 firmware 소프트웨어를 개발하는 방법으로 구현하고자 한다. 본 논문에서는 먼저 TMS320C80을 바탕으로 한 하드웨어 구현에 관해 논의한다. 하드웨어의 구조는 TMS320C80과 시스템 메모리로의 DRAM, 오디오 입력부인 ADC, 입력 데이터를 효과적으로 사용하기 위한 FIFO menory, 오디오 출력용인 dac, 디버깅 및 통신포트로 USB, RS-232,LPT와 MPEG-2 encoding보드 등 다른 보드와 연계를 위한 local-bus를 위한 dual port ram으로 구성된다. 오디오 입력은 최대 24bit 48kHz sampling까지 받을 수 있다.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.811-814
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• 2000

본 논문에서는 AMR 음성 부호화 알고리즘을 분석하고 C프로그램 최적화 과정을 거친후 OakDSPCore?를 기반으로 설계된 C&S Technology사의 CSD17C00A칩을 이용하여 전과정을 어셈블리어로 실시간 구현 하였다. 구현된 코덱은 최대의 계산량을 요구하는 6.7kbps 모드일때, 인코더부분이 최대 20.6MIPS 이며 디코더부분은 약 2.7MIPS 의 복잡도를 나타낸다. 사용된 프로그램 메모리는 약 21.97kwords, 데이터 RAM 메모리는 약 6.64kwords를 가지며 데이터 ROM 메모리는 약 15.1kwords 이다. 구현된 코덱은 최대 약23.29MIPS의 복잡도를 가지고 있으므로 40MIPS의 처리용량을 가지는 CSD17C00A 를 이용한 보드상에서 실시간 동작이 가능함을 확인하였다. 구현된 프로그램은 3GPP에서 제공하는 21개의 test 벡터들을 통하여 bit-exact 함을 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.264-267
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• 2004

[ $Bi_{3.25}La_{0.75}Ti_3O_{12}$ ] (BLT) thin films were prepared by using metal organic decomposition method onto the $LaNiO_3$ (LNO) bottom electrode. Both the structure and morphology of the films were analyzed by x-ray diffraction (XRD) and atomic force microscope (AFM). Even at low temperatures ranging from 450 to $650^{\circ}C$, the BLT thinfilms were successfully deposited on LNO bottom electrode and exhibited (117) orientation. The BLT thin films annealed as low as $600^{\circ}C$ showed excellent ferroelectricity, higher remanent polarization and no significant degradation of switching charge at least up to $5{\times}10^9$ switching cycles at a frequency of 100 kHz and 5 V. For the annealing temperature of $600^{\circ}C$, the remanent polarization Pr and coercive field were $23.5\;C/cm^2$ and 120 kV/cm, respectively.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.08a
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• pp.165-168
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• 1998

제안하고 있는 CSD17C00 chip은 C&S technology에서 개발한 것으로, 음성 신호 처리를 위해 범용으로 구현되었으며, 16 bit 40 MIPS DSP group OAK DSP Core를 포함, 이에 Miscellaneous Logic, Serial Port, Host Interface, Timer, Compander 의 5가지 Peripherals 과 범용 I/O Ports 로 설계되었다. 1차적으로 CSD17C00 Chip 의 성능을 점검하였다. 그 결과, 응용 프로그램은 28MIPS의 계산속도를 갖으며, 프로그램 ROM 크기는 8.85KWords 이고, 10KWords 의 데이터 ROM 과 4KWords 데이터 RAM을 필요로 한다. CSD17C00 CHIP은 멀티미디어 통신용 VOCODER 개발을 위한 범용성을 갖추고 있으며, VOCODER 용 S/W 개발 환경 및 H/W 구조가 여타 범용 DSP에 비해편의성고 K합리성을 제공하도록 설계되어 있다. 따라서, 이를 이용한다면, 멀티 미디어 통신용 VOCODER, INTERNET PHONE CO-PROCESSOR, DIGITAL RECODER, MPEG AUDIO ENCODER & DECODER 등 다양한 제품으로의 응용이 가능할 것으로 전망된다.

• Journal of the Korean Mathematical Society
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• v.45 no.2
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• pp.377-392
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• 2008

Let X be a real reflexive Banach space with a uniformly $G\hat{a}teaux$ differentiable norm, C a nonempty closed convex subset of X, T : C $\rightarrow$ X a continuous pseudocontractive mapping, and A : C $\rightarrow$ C a continuous strongly pseudocontractive mapping. We show the existence of a path ${x_t}$ satisfying $x_t=tAx_t+(1- t)Tx_t$, t $\in$ (0,1) and prove that ${x_t}$ converges strongly to a fixed point of T, which solves the variational inequality involving the mapping A. As an application, we give strong convergence of the path ${x_t}$ defined by $x_t=tAx_t+(1-t)(2I-T)x_t$ to a fixed point of firmly pseudocontractive mapping T.