• Journal of Electrical Engineering and Technology
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• v.11 no.4
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• pp.1020-1026
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• 2016

Motion estimation (ME) algorithms supporting quarter-pixel accuracy have been recently introduced to retain detailed motion information for high quality of video in the state-of-the-art video compression standard of H.264/AVC. Conventional sub-pixel ME algorithms in the spatial domain are faced with a common problem of computational complexity because of embedded interpolation schemes. This paper proposes a low-complexity sub-pixel motion estimation algorithm in the transform domain utilizing shifting matrix. Simulations are performed to compare the performances of spatial-domain ME algorithms and transform-domain ME algorithms in terms of peak signal-to-noise ratio (PSNR) and the number of bits per frame. Simulation results confirm that the transform-domain approach not only improves the video quality and the compression efficiency, but also remarkably alleviates the computational complexity, compared to the spatial-domain approach.

• Journal of IKEEE
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• v.13 no.4
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• pp.110-115
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• 2009

The motion compensation is the most time-consuming and complex unit in the H.264 decoder. The performance of the motion compensation is determined by the calculation of pixel interpolation. The quarter-pixel interpolation is achieved using 6-tap horizontal or vertical FIR filters for luminance data and bilinear FIR filters for chroma data. We propose the architecture for interpolation of luminance and chroma data in H.264 decoders. It is composed of dual-channel pipelined processing elements and can interpolate integer-, half- and quarter-pixel data. The number of the processing cycles is different depending on the position. The processing elements are composed of adders and shifters to reduce the complexity while the accuracy of the pixel data are maintained. We design interpolators for luminance and chroma data using Verilog-HDL and verify the function and performance by implementing using an FPGA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.2
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• pp.372-379
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• 2015

The latest video compression standard (such as H.264/AVC and HEVC) utilizes quarter-pel accuracy motion estimation in order to retain detailed motion information. Many sub-pixel motion estimation algorithms used in the spatial domain usually encounters increment of computational complexity due to embedded interpolation algorithm. In this paper, an approach to measure sub-pixel accuracy motion estimation in frequency domain using shifting matrix is proposed. Complexity can be reduced utilizing shifting matrix algorithm in frequency domain and simulation results demonstrate not only higher PSNR but lower bit rates than spatial domain algorithms.

• ETRI Journal
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• v.30 no.4
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• pp.506-515
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• 2008

The H.264/AVC standard has adopted new coding tools such as intra-prediction, variable block size, motion estimation with quarter-pixel-accuracy, loop filter, and so on. The adoption of these tools enables an H.264/AVC-coded bitstream to have more information than was possible with previous standards. In this paper, we propose an effective spatial error concealment method with low complexity in H.264/AVC intra-frame. From information included in an H.264/AVC-coded bitstream, we use prediction modes of intra-blocks to recover a damaged block. This is because the prediction direction in each prediction mode is highly correlated to the edge direction. We first estimate the edge direction of a damaged block using the prediction modes of the intra-blocks adjacent to a damaged block and classify the area inside the damaged block into edge and flat areas. Our method then recovers pixel values in the edge area using edge-directed interpolation, and recovers pixel values in the flat area using weighted interpolation. Simulation results show that the proposed method yields better video quality than conventional approaches.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.527-533
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• 2008

Motion compensation always produces the principal bottleneck in the real-time high quality video applications. Therefore, a fast dedicated hardware is needed to perform motion compensation in the real-time video applications. In many video encoding methods, the frames are partitioned into blocks of Pixels. In general, motion compensation predicts present block by estimating the motion from previous frame. In motion compensation, the higher pixel accuracy shows the better performance but the computing complexity is increased. In this paper, we studied an architecture of motion compensator suitable for H.264/AVC encoder that supports quarter-pixel accuracy. The designed motion compensator increases the throughput using transpose array and 3 6-tap Luma filters and efficiently reduces the memory access. The motion compensator is described in VHDL and synthesized in Xilinx ISE and verified using Modelsim_6.1i. Our motion compensator uses 36-tap filters only and performs in 640 clock-cycle per macro block. The motion compensator proposed in this paper is suitable to the areas that require the real-time video processing.