• Title/Summary/Keyword: Quantization Error

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Realization of the multi-phase level CGH according to the multi-channel encoding method using a PAL-SLM (PAL-SLM을 이용한 다채널 부호화 방법에 따른 다위상형 CGH의 광학적 구현)

  • Jung, Jong-Rae;Baek, Woon-Sik;Kim, Jung-Hoi;Kim, Nam
    • Korean Journal of Optics and Photonics
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    • v.15 no.4
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    • pp.299-308
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    • 2004
  • We proposed more efficient encoding methods that can design a multi-channel multi-level phase only computer-generated hologram(CGH) that can reconstruct many objects simultaneously without a conjugate image. We used a fabrication technique for the pixel oriented CGH for designing the pattern of the proposed multi-channel CGH. We investigated the difference of the optical efficiency(η), mean square error(MSE) and signal-to-noise ratio(SNR) of multi-channel CGHs that were designed by three kinds of encoding methods according to the number of quantization phase levels, and we estimated the performance of the pattern of the proposed multi-channel CGH. Generally, as the number of input objects' reference patterns stored in the CGH is increased, the reconstruction quality of the CGH is degraded. But we observed through computer simulation that the diffraction efficiency of the 1-ch CGH is 70%, and those of the 2-ch, 4-ch, 8-ch CGHs are 62%, 62% and 63%. Therefore we found that the diffraction efficiencies of the multi-channel CGHs using the newly proposed encoding method are similar to that of 1-ch CGH. We implemented the CGH optically using a liquid crystal spatial light phase modulator that consisted of a PAL-SLM efficiently coupled with a XGA type LCD by an optical lens and an LD for illuminating the LCD. We discussed the output images that are reconstructed from the PAL-SLM.

Hardware Implementation of Real-Time Blind Watermarking by Substituting Bitplanes of Wavelet DC Coefficients (웨이블릿 DC 계수의 비트평면 치환방법에 의한 실시간 블라인드 워터마킹 및 하드웨어 구현)

  • 서영호;김동욱
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.3C
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    • pp.398-407
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    • 2004
  • In this paper, a blind watermarking method which is suitable to the video compression using 2-D discrete wavelet transform was proposed and implemented into the hardware using VHDL(VHSIC Hardware Description Language). The goal of the proposed watermarking algorithm is the authentication about the manipulation of the watermark embedded image and the detection of the error positions. Considering the compressed video image, the proposed watermarking scheme is unrelated to the quantization and is able to concurrently embed or extract the watermark. We experimentally verified that the lowest frequency subband(LL4) is not sensitive to the change in the spatial domain, so LL4 subband was selected for the mark space. And the combination of the bitplanes which has the properties of both the minimum degradation of the image and the robustness was chosen as the embedded Point in the mark space in LL4 subband. Since we know the watermark embedded positions and the watermark is embedded by not varying the value but changing the value, the watermark can be extracted without the original image. Also, for the security when exposing the watermark embedded position, we embed the encrypted watermark by the block cipher. The proposed watermark algorithm shows the robustness against the general image manipulation and is easily transplanted into the image or video compressor with the minimal changing in the structure. The designed hardware has 4037 LABs(24%) and 85 ESBs(3%) in APEX20KC EP20K400CF672C7 FPGA of Altera and stably operates in 82MHz clock frequency.

Hardware Design of In-loop Filter for High Performance HEVC Encoder (고성능 HEVC 부호기를 위한 루프 내 필터 하드웨어 설계)

  • Park, Seungyong;Im, Junseong;Ryoo, Kwangki
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.2
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    • pp.335-342
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    • 2016
  • This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.

Hardware Design of High Performance In-loop Filter in HEVC Encoder for Ultra HD Video Processing in Real Time (UHD 영상의 실시간 처리를 위한 고성능 HEVC In-loop Filter 부호화기 하드웨어 설계)

  • Im, Jun-seong;Dennis, Gookyi;Ryoo, Kwang-ki
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.10a
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    • pp.401-404
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    • 2015
  • This paper proposes a high-performance in-loop filter in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. HEVC uses in-loop filter consisting of deblocking filter and SAO(Sample Adaptive Offset) to solve the problems of quantization error which causes image degradation. In the proposed in-loop filter encoder hardware architecture, the deblocking filter and SAO has a 2-level hybrid pipeline structure based on the $32{\times}32CTU$ to reduce the execution time. The deblocking filter is performed by 6-stage pipeline structure, and it supports minimization of memory access and simplification of reference memory structure using proposed efficient filtering order. Also The SAO is implemented by 2-statge pipeline for pixel classification and applying SAO parameters and it uses two three-layered parallel buffers to simplify pixel processing and reduce operation cycle. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 205K logic gates in TSMC 0.13um process. At 110MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 30fps in realtime.

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An Adaptive Intra Coding Technique Using 1-D and 2-D Integer Transforms (1차원 및 2차원 정수 변환을 이용한 적응적 화면내 코딩 기법)

  • Park, Min-Cheol;Kim, Dong-Won;Moon, Joo-Hee
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.46 no.5
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    • pp.66-79
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    • 2009
  • In this paper, we propose a new adaptive intra coding technique using 1-D and 2-D integer transforms for improving coding efficiency of H.264/AVC. Proposed technique selects the most effective transform and prediction mode for each block after processing 1-D and 2-D transforms of all prediction modes. In case of using 1-D transform, $4{\times}4$ block is divided into four $1{\times}4$ or $4{\times}1$ subblocks and then each subblock is predicted and subtracted by using the decoded subblock located at the nearest position in the direction of prediction. After prediction error subblock is processed by 1-D transform and quantization, four subblocks are merged back into original $4{\times}4$ block and then, reordered as 1-D signal by a DC biased zigzag scanning pattern according to the prediction mode. Finally, comparing the coding efficiency between bitstreams based on 1-D transform and conventional 2-D transform, prediction mode and quantized coefficients for each block are decided and corresponding quantized coefficients are transmitted. Experimental results show that the proposed adaptive technique increases 0.34dB in BD-PSNR and decreases 4.03% in BD-Bitrate on the average compared with H.264/AVC.

Improved Downlink Performance of Transmit Adaptive Array applying Transmit Antenna Selection (적응형 송신 빔 성형 시스템의 순방향 링크 성능 향상을 위한 송신 안테나 선택 방식의 적용)

  • Ahn, Cheol-Yong;Kim, Dong-Ku
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.3A
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    • pp.111-118
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    • 2003
  • The transmit adaptive array requires the forward link channel information for evaluating the optimum transmit weight vector in which a feedback channel provides transmitter with the forward link channel information. The larger transmit adaptive array is, the higher required rate of feedback channel is. Therefore we consider the system that the N-transmit antenna system is expanded to the 2N-transmit antenna system, while the feedback channel is maintained as that of N-transmit antenna system. The increase of the number of antennas can produce the additional diversity gain, however the insufficient feedback bits assigned to each antenna aggravates the quantization error. In this paper, we propose the transmit antenna selection in order to improve the performance of transmit adaptive array having an insufficient feedback channel information. The effective method to transmit the weight vector is also introduced. System performances are investigated for the case of N=4 corresponding to the antenna selection diversity schemes on the flat fading channel and the multipath fading channel. The simulation results show that the proposed scheme can improve the system performance by 1 dB when the N is expanded to the 2N, while the feedback channel is restricted to that of N-transmit antenna system.