• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.39-49
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• 2011

Turbo code needs long decoding time because of iterative decoding. To communicate with high speed, we have to shorten decoding time and it is possible with parallel process. But memory contention can cause from parallel process, and it reduces performance of decoder. To avoid memory contention, QPP interleaver is proposed in 2006. In this paper, we propose MDF method which is fit to QPP interleaver, and has relatively short decoding time and reduced logic. And introduce the design of MAP decode module using MDF method. Designed decoder is targetted to FPGA of Xilinx, and its throughput is 80Mbps maximum.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.83-88
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• 2008

The QPP interleaver has been gaining attention since it provides contention-free interleaving functionality for high speed parallel turbo decoders. In this paper we first show that the quadratic term $f_2x^2%K$ of $f(x)=(f_1x+f_2x^2)%K$, the address generating function, is periodic. We then introduce a low-power address generator which utilizes this periodic characteristic. This generator follows the conventional method to generate the interleaving addresses and also to save the quadratic term values during the first half of the first period. The saved values are then reused for generating further interleaved addresses, resulting in reduced number of logical operations. Power consumption is reduced by 27.38% in the design with fixed-K and 5.54% in the design with unfixed-K on average for various values of K, when compared with the traditional designs.