• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
• /
• pp.80-83
• /
• 2001

이족로봇이 stand-alone 형태를 가지기 위해서는 기계적인 구조가 중요할 뿐만 아니라 하드웨어시스템이 간결하게 잘 설계되어야 한다. 이렇게 하드웨어시스템이 가볍고 간결하여 설계되어야 쉽게 로봇에 장착할 수가 있다. 본 논문에서는 FPGA(Field Programmable Gate Array)를 이용해 모터 제어기를 구성해서 이족로봇을 설계하는 방법을 다루고자 한다. 본 논문에서 구성하는 하드웨어 시스템은 메인 CPU로 AM186ES를 사용하며 FPGA는 Altera사의 FLEX EPF10K20TC144-3을 사용하였다. 이와 같이 FPGA를 사용하는 하드웨어시스템은 기본적으로 VHDL언어를 사용하여 유연하게 하드웨어를 구성 할 수 있으며, 이족로봇의 여러 가지 보행 알고리즘에 능동적으로 대처할 수 있다. 뿐만 아니라 하드웨어가 간단해 지면서 가볍고 전력소모가 적으며 신뢰성 있는 시스템을 구축할 수 있다.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2003년도 ICCAS
• /
• pp.1022-1027
• /
• 2003

The Motion controllers provide the sophisticated performance and enhanced capabilities we can see in the movements of robotic systems. Several types of motion controllers are available, some based on the kind of overall control system in use. PLC (Programmable Logic Controller)-based motion controllers still predominate. The many peoples use MCU (Micro Controller Unit)-based board level motion controllers and will continue to in the near-term future. These motion controllers control a variety motor system like robotic systems. Generally, They consist of large and complex circuits. PLC-based motion controller consists of high performance PLC, development tool, and application specific software. It can be cause to generate several problems that are large size and space, much cabling, and additional high coasts. MCU-based motion controller consists of memories like ROM and RAM, I/O interface ports, and decoder in order to operate MCU. Additionally, it needs DPRAM to communicate with host PC, counter to get position information of motor by using encoder signal, additional circuits to control servo, and application specific software to generate a various velocity profiles. It can be causes to generate several problems that are overall system complexity, large size and space, much cabling, large power consumption and additional high costs. Also, it needs much times to calculate velocity profile because of generating by software method and don't generate various velocity profiles like arbitrary velocity profile. Therefore, It is hard to generate expected various velocity profiles. And further, to embed real-time OS (Operating System) is considered for more reliable motion control. In this paper, the structure of chip-based precision motion controller is proposed to solve above-mentioned problems of control systems. This proposed motion controller is designed with a FPGA (Field Programmable Gate Arrays) by using the VHDL (Very high speed integrated circuit Hardware Description Language) and Handel-C that is program language for deign hardware. This motion controller consists of Velocity Profile Generator (VPG) part to generate expected various velocity profiles, PCI Interface part to communicate with host PC, Feedback Counter part to get position information by using encoder signal, Clock Generator to generate expected various clock signal, Controller part to control position of motor with generated velocity profile and position information, and Data Converter part to convert and transmit compatible data to D/A converter.

• 한국정보처리학회논문지
• /
• 제7권1호
• /
• pp.135-145
• /
• 2000

MMS(Manufacturing Message Specification)는 PLC, NC, 로봇 등과 같이 서로 다른 제조회사의 서로 다른 단위제어기기 제품들간에 통신할 수 있는 ISO/IEC 9506으로 표준화된 공장자동호용 프로토콜이며 OSI 참조 모델의 최상위 층인 응용계층 프로토콜에 해당된다. 본 논문은 MMS를 TCP/IP상에서 동작할 수 있도록 유닉스 환경에서 ASNSI-C 언어로 구현하고, 이 구현된 프로토콜을 JNI(Java Native Interface)를 이용해 JAVA 클래스화한다. JAVA 클래스화함으로써 기존에 제공되는 MMS 라이브러리를 이용하는데 있어 표준화되지 않은 서로 다른 API를 이용하는데 어려움과 GUI를 구현하는데 어려움을 극복하는 기본을 제공한다. 그리고 구현된 JAVA 클래스화된 MMS 라이브러리를 인터넷의 WWW상에서 동작시킬 수 있도록 자동화된 PCB(Printed Circuit Board) 조립라인을 대상 모델로 선정하여 응용 프로그램을 작성하여 구현된 JNI를 이용한 MMS가 인터넷상에서 동작하여 사용자에게 일괄성있는 인터페이스를 제공하는 웹 브라우저를 통해 RMD(Real Manufacturing Device)를 동작${\cdot}$제어${\cdot}$감시할 수 있음을 보여준다.

• 센서학회지
• /
• 제7권2호
• /
• pp.124-130
• /
• 1998

독립적인 로보트나 자동차 제어 응용을 위하여 고속 3-D 비젼시스템들은 매우 중요하다. 이 논문은 다음과 같은 세가지 과정으로 구성되는 stereo vision process 개발에 대하여 논술한다 : 왼쪽과 오른쪽 이미지의 edges 추출, matching coresponding edges와 3-D map의 계산. 이 process는 VME 150/40 Imaging Technology vision system에서 이루어졌다. 이것은 display, acqusition, 4Mbytes image frame memory와 세 개의 연산 카드로 구성되는 modular system이다. 40 MHz로 작동하는 프로그래머불 연산 모듈은 $64{\times}32$ bit instruction cache와 두개의 $1024{\times}32$ bit RAM을 가진 TMS320C31 DSP에 기초를 두고 있다. 그것들은 각각 512 Kbyte static RAM, 4 Mbyte image memory, 1 Mbyte flash EEPROM과 하나의 직렬 포트로 구성되어있다. 모듈간의 데이터 전송과 교환은 8 bit globalvideo bus와 세 개의 local configurable pipeline 8 bit video bus에 의하여 이루어졌고, system management를 위하여 VME bus가 쓰였다. 두 개의 DSP는 왼쪽 및 오른쪽 이미지 edges 검출을 위하여 쓰였고 마지막 processor는 matching process와 3-D 연산에 사용되었다. $512{\times}512$픽셀 이미지에서 이 센서는 scene complexity에 따라 1Hz정도의 조밀한 3-D map을 생성했다. 특수목적의 multiprocessor card들을 사용하면 결과를 향상시킬 수 있을 것이다.

• 한국지능시스템학회:학술대회논문집
• /
• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
• /
• pp.975-976
• /
• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}