• 한국군사과학기술학회지
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• 제15권6호
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• pp.812-819
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• 2012

Interference and jamming are becoming increasing concern to a radar system nowdays. AESA(Active Electronically Steered Array) antennas and adaptive beamforming(ABF), in which antenna beam patterns can be modified to reject the interference, offer a potential solution to overcome the problems encountered. In this paper, we've developed a planar active phased array radar system, in which ABF, target detection and tracking algorithm operate in real-time. For the high output power and the low noise figure of the antenna, we've designed the S-band TRMs based on GaN HEMT. For real-time processing, we've used wavelenth division multiplexing technique on fiber optic communication which enables rapid data communication between the antenna and the signal processor. Also, we've implemented the HW and SW architecture of Real-time Signal Processor(RSP) for adaptive beamforming that uses SMI(Sample Matrix Inversion) technique based on MVDR(Minimum Variance Distortionless Response). The performance of this radar system has been verified by near-field and far-field tests.

• 전자공학회논문지C
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• 제34C권7호
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• pp.28-37
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• 1997

In this paper, we designed a motion estimator for MPEG-2 video coder using VHDL. Motion estimation is indispensable for encoding MPEG 2 video. Motion estimation takes over 50% computation power of video encoding 37 frames per second and is suitable for real-time processing. The number of data accesses for computation is fewer than 2 times compared with that of old one. This makes slower memory module available. We minimize input pins to migrate input data through PEs. This processor can compute various motio estimation modes at one calculation that is supported by MPEG-2 video standard. Also independent control architecture makes this processor a single processor or a sub module in amultimedia chip.

• 대한전자공학회논문지
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• 제24권6호
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• pp.1040-1048
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• 1987

We propose a hardware architecture called Multiring which is applicable for various geometrical operations on rectilinear objects such as design rule checking in VLSI layout and many image processing operations including noise suppression and coutour extraction. It has both a fast execution speed and extremely high flexibility. The whole architecture is mainly divided into four parts` I/O between host and Multiring, ring memory, linear processor array and instruction decoder. Data transmission between host and Multiring is bit serial thereby reducing the bandwidth requirement for teh channel and the number of external pins, while each row data in the bit map stored in ring memory is processed in the corresponding processor in full parallelism. Each processor is simultaneously configured by the instruction decoder/controller to perform one of the 16 basic instructions such as Boolean (AND, OR, NOT, and Copy), geometrical(Expand and Shrink), and I/O operations each ring cycle, which gives Multiring maximal flexibility in terms of design rule change or the instruction set enhancement. Correct functional behavior of Multiring was confirmed by successfully running a software simulator having one-to-one structural correspondence to the Multiring hardware.

• 디지털산업정보학회논문지
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• 제8권1호
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• pp.117-123
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• 2012

This paper implements mobile Worldwide Interoperability for Microwave Access (WiMAX) receiver using Software Defined Radio (SDR) technology. SDR system is difficult to implement on the mobile handset because of restrictions that are computing power and under space constraints. The implemented receiver processes mobile WiMAX software modem on Open Multimedia Application Platform (OMAP) System on Chip (SoC) and Field Programmable Gate Array (FPGA). OMAP SoC is composed of ARM processor and Digital Signal Processor (DSP). ARM processor supports Single Instruction Multiple Data (SIMD) instruction which could operate on a vector of data with a single instruction and DSP is powerful image and video accelerators. For this reason, we suggest the possibility of SDR technology in the mobile handset. In order to verify the performance of the mobile WiMAX receiver, we measure the software modem runtime respectively. The experimental results show that the proposed receiver is able to do real-time signal processing.

• Journal of Information Processing Systems
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• 제7권1호
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• pp.85-92
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• 2011

This paper shows an effective partitioning of static global row/column buses for tightly coupled 2D mesh-connected small processor arrays ("mesh", for short). With additional O(n/m (n/m + log m)) time slowdown, it enables the mesh of size $m{\times}m$ with static row/column buses to simulate the mesh of the larger size $n{\times}n$ with reconfigurable row/column buses ($m{\leq}n$). This means that if a problem can be solved in O(T) time by the mesh of size $n{\times}n$ with reconfigurable buses, then the same problem can be solved in O(Tn/m (n/m + log m)) time on the mesh of a smaller size $m{\times}m$ without a reconfigurable function. This time-cost is optimal when the relation $n{\geq}m$ log m holds (e.g., m = $n^{1-\varepsilon}$ for $\varepsilon$ > 0).

• 대한전자공학회논문지
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• 제23권3호
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• pp.340-344
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• 1986

This paper shows that we can design a vector-coordinate rotation processor and obtain the approximate evaluations of sine and cosine based upon the use of residue number systems. The algorithm results in the considerable improvement of the computation speed when compared to CORDIC algorithm. The results from computer simulation show that the mean error of sine and cosine is 0.0025 and the mean error of coordinate rotation arithmatic is 0.65. Also, the proposed processor has the efficiency for the design and fabrication of integrated circuit, because it consists of the array of idecntially structured look-up tables.

• 한국통신학회논문지
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• 제19권10호
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• pp.2043-2052
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• 1994

본 논문에서는 근접한 Processing Element(PE)들간의 통신 부담을 경감시켜 영상신호를 실시간 처리할 수 있는 새로운 병렬처리 방식 ASIC 구조를 설계한다. 하나의 Sliding Memory Plane (SliM) Image Processor chip을 병렬처리 방식을 사용 $3\times3$ PE를 격자 형태로 연결한다. 제안하는 Image Processor를 구현할 수 있다. Sliding 개념은 별도의 보조 프로세서나 DMA를 사용치 않고 또한 PE들을 interupt 걸지 않고 모든 화소가 이웃 PE로 이동됨을 의미한다. 따라서 근접 통신과 계산이 동시에 일어나 기존의 격자 연결 병렬 컴퓨터의 결정적 단점인 근접 통신 부담을 경감시킬 수 있다. 또한 하나의 PE에 두 개의 입출력용 레지스터 plane을 사용, buffer를 제공하여 입출력 부담을 감소시킨다. SliM Image Processor에서는 단지 4개의 통신 link만으로 8가지 방향의 통신경로를 제공하는 by-passing path에 의해 통신 부담없이 대각선 통신을 수행할 수 있다. 제안하는 유일한 특성들로 인해 영상 신호 처리시 성능을 향상시킬 수 있다. 영상신호 처리를 위한 알고리즘들을 효율적으로 수행키 위한 PE, Image Processor 구조 및 명령어를 설계한다.

• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• 한국정보과학회논문지:시스템및이론
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• 제27권5호
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• pp.475-484
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• 2000

최근에 전자 버스 대신에 광 버스를 사용하여 버스의 대역폭을 늘리고 하드웨어의 복잡도를 줄이기 위한 처리기 배열의 구조가 다수의 문헌에서 제안되었다. 본 논문에서는 먼저 슬롯된 광 버스를 갖는 선형 처리기 배열(LASOB) 상에서 괄호 매칭 문제에 대한 상수 시간 알고리즘을 제안한다. 다음에 이 알고리즘을 사용하여 길이 n의 대수 식이 주어지면 n개의 처리기를 갖는 LASOB 상에서 상수 시간에 계산 트리 형식을 생성하는 비용이 최적인 병렬 알고리즘을 제안한다. 아직 임의의 병렬 컴퓨터 모델에서 이 문제에 대한 상수 시간에 수행되는 비용 최적인 병렬 알고리즘은 알려지지 않고 있다.

• 한국음향학회지
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• 제21권7호
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• pp.606-613
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• 2002

본 논문에서는 수중에서 송신 빔 형성기를 이용한 고속 데이터 전송 기법을 연구하였다. 또한 범용 디지털 신호처리 프로세서와 다수의 디지탈-아날로그 변환기를 이용한 시험용 송신단을 설계 및 구현하였으며, 구현된 시스템을 이용하여 수조에서 실험을 수행하여 그 성능을 분석하였다. 이때 실험 과정을 단순화하기 위하여 채널 코딩 및 등화기 (equalizer) 등과 같은 과정은 생략하였고, 간장 간단한 디지털 통신 변조 기법인 OOK(On-Off keying) 기법을 사용하였다. 실험 결과 5개의 하이드로폰 송신 어레이를 사용한 경우에 1개만 사용했을 때보다 오차율 10/sup -2/을 기준으로 전송 속도가 약 3배 향상되었으며, 실험에 사용된 수조에서 음성 신호 전송을 위해 400 bps 정도까지 가능함을 확인하였다.