• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.430-433
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• 1999

Woo[8]proposed dual-token based fault-tolerant scheduling algorithm in multiprocessor environment for resolving the problem of old systems that have a central dispatcher processor. However, this algorithm does not present token allocation algorithm in detail when central dispatcher processor has failed. In this paper, we propose a fault detection algorithm and processor selection algorithm for token allocation when central dispatcher processor has failed.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.17 no.32
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• pp.145-154
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• 1994

In this paper, monitoring processor in a circuit switched network is considered. Monitoring processor monitors communication links, and offers a grade of service in each link to controller. Such an information is useful for an effective maintenance of system. Two links with nonsymmetric system Parameters are considered. each link is assumed independent M/M/1/1 type. The Markov process is introduced to compute busy and idle portions of monitoring processor and monitored rate of each link. Inter-idle times and inter-monitoring times of monitoring processor between two links are respectively computed. A recursive formula is introduced to make computational procedure rigorous.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.12
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• pp.1-10
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• 1994

In this paper, we propose a processor allocation algorithm using the PGG(Packed Gray code Group) for the MIMD hypercube. The number of k-D subcubes in an n-cube is C(n.k) en-k. When the PGG is employed in the processor allocation, C(n, k) PGG's are required to recognize all the k-D subcubes in an n-cube. from the simulation we find that the capability of processor allocation using only 40% of C(n, k) PGG's is about the same as that of the allocation using all the PGG's.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.74-76
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• 2007

This paper presents the hardware design of a 32bit floating point based processor. The processor can perform nonlinear functions such as sinusoidal functions, exponential functions, and other nonlinear functions. Using the Taylor series and the Newton - Raphson method, nonlinear functions are approximated. The processor is actually embedded on an FPGA chip and tested. The numerical accuracy of the functions is compared with those computed by the MATLAB.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.5-8
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• 2002

In this paper, we are designed and verified a FFT/IFFT processor that is possible from the wireless LAN environment which is adopted international standard of the IEEE802.11a. The proposed architecture of the FFT/IFFT has Radix-2 64point SDF(single-path delay feedback) Pipeline technique and DIF(Decimation in Frequenct) structure. The FFT/IFFT processor has each 8 bit complex input-output and 6 bit Twiddle factor. we used Max-PlusII for simulation and can see that processor is properly operated

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.201-204
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• 1987

To improve the reliability of boiler controller of a power plant, FTCS(Fault Tolerant Control System) is proposed. We studied to implement a Multi-processor scheme for FTCS. This paper presents the total system to experiment the performance of FTCS and the Multi-processor scheme implemented.

• Journal of the Korean Institute of Navigation
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• v.14 no.4
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• pp.31-39
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• 1990

A systematic methodology for efficient implementation of processor arrays from regular iterative algorithms is proposed. One of the modern parallel processing array architectures is the Systolic arrays and we use it for processor arrays on this paper. On designing the systolic arrays, there are plenty of mapping functions which satisfy necessary conditions for its implementation to the time-space domain. In this paper, we sue a few conditions to reduce the total number of computable mapping functions efficiently. As a results of applying this methodology, efficient designs of systolic arrays could be done with considerable saving on design time and efforts.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.08a
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• pp.341-344
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• 2000

The 0-1 knapsack processor performing dynamic programming is designed and implemented on a programmable logic device. Three types of a processor, each with different behavioral models, are presented, and the operation of a processor of each type is verified with an instance of the 0-1 knapsack problem.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.2043-2052
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• 1994

This paper proposes a new parallel ASIC architecture for real-time image processing to reduce inter-processing element (inter-PE) communication overhead, called a Sliding Memory Plane (SliM) Image Processor. The Slim Image Processor consists of $3\times3$ processing elements (PEs) connected by a mesh topology. With easy scalability due to the topology. a set of SliM Image Processors can form a mesh-connected SIMD parallel architecture. called the SliM Array Processor. The idea of sliding means that all pixels are slided into all neighboring PEs without interrupting PEs and without a coprocessor or a DMA controller. Since the inter-PE communication and computation occur simultaneously. the inter-PE communication overhead, significant disadvantage of existing machines greatly diminishes. Two I/O planes provide a buffering capability and reduce the date I/O overhead. In addition, using the by-passing path provides eight-way connectivity even with four links. with these salient features. SliM shows a significant performance improvement. This paper presents architectures of a PE and the SliM Image Processor, and describes the design of an instruction set.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.123.2-123.2
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• 2010

Fuel Cell cogeneration system is a promising technology for generating electricity and heat with high efficiency of low pollutant emission. We have been developed 5kW class fuel cell cogeneration system for commercial and residential application. The fuel processor is a crucial part of producing hydrogen from the fossil fuels such as LNG and LPG. The 5kW class high efficiency fuel processor consists of steam reformer, CO shift converter, CO preferential oxidation(PrOx) reactor, burner and heat exchanger. The one-stage CO shift converter process using a metal oxide catalyst was adopted. The efficiency of 5 kW class fuel processor shows 75% based on LHV. In addition, for the purpose of continuous operation with load fluctuations in the commercial system for residential use, load change of fuel processor was tested. Efficiency of 30%, 50%, 70% and 100% load shows 75%, 75%, 73% and 72%(LHV), respectively. Also, during the load change conditions, the product gas composition was stable and the outlet CO concentration was below 5 ppm. The Fuel processor operation was carried out in residential fuel cell cogeneration system with fuel cell stack under dynamic conditions. The 5kW class fuel processor have been evaluated for long-term durability and reliability test including with improvement in optimal operation logic.