• 한국철도학회:학술대회논문집
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• 한국철도학회 2011년도 정기총회 및 추계학술대회 논문집
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• pp.2348-2356
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• 2011

In recent years, many researches for DC power distributed system (PDS) are being preformed and the importance of the DC PDS is more and more emphasized. Furthermore, in the railway system, the DC PDS is used in subway station lighting, facilities, etc. In the DC PDS, DC bus voltage instability may be occurred by the operation of multiple parallel loads such as pulsed power load, motor drive system, and constant power loads. Thus, good quality and high reliability for electric power are required and voltage bus conditioner (VBC) may be used the DC PDS. The VBC is a DC/DC converter for mitigation of the bus transients. In this paper, adaptive controller is designed. The simulation results by PSIM are presented for validating the proposed control algorithm.

• 한국전자파학회논문지
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• 제17권2호
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• pp.213-220
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• 2006

본 논문은 결합제거용 커패시터가 금속선을 포함한 타 집중 소자들과 함께 장하될 경우 PCB power-bus에 미치는 영향을 살펴본다. 향상된 PCB EMC 대책을 준비하는 일환으로 장하된 PCB power-bus 다양한 경우에 대해 전자장과 임피던스가 엄밀하게 계산되고 결과 분석이 이뤄진다.

• Journal of Electrical Engineering and Technology
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• 제11권1호
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• pp.76-85
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• 2016

This paper presents a method of decision on where bus splitting is needed to reduce fault current level of power systems and to satisfy the fault current constraints. The method employs a modified fault current constrained optimal power flow (FCC-OPF) with X variables for the candidate locations of splitting and for decision making on whether to split or not, it adopts soft-discretization by augmenting inversed U-shaped penalty terms. Also, this paper discusses the procedure on the adequate selection of bus splitting locations based on the results of the modified FCC-OPF, to reduce the total number of the actions taken.

• 한국통신학회논문지
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• 제36권12B호
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• pp.1548-1555
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• 2011

UDSM(Ultra Deep SubMicron)기술을 이용한 시스템 온-칩 설계 시 가창 중요한 설계 요소는 버스 상에서의 전력소모와 지연시간을 최소화 하는 것이다. 인접한 선에서 발생되는 crosstalk는 전파 지연을 발생시키는데 지대한 영향을 미치며, 이를 제거하거나 최소화 시키는 일은 SoC(System on a Chip) 설계에서 시스템의 신뢰성 및 성능 향상과 직결된다. 기존의 방법들은 주로 crosstalk 지연이나 버스 스위칭 횟수 중 하나 만을 최소화하는 방법이 제안되었다. 본 논문에서는 인코딩 적용 4 비트 클러스터 상의 버스 스위칭 횟수에 따라 crosstalk과 스위칭 횟수를 동시에 최소화 할 수 있도록 "invert" 기능과 "logic-convert" 기능을 적응적으로 선택하는 새로운 인코딩 기법을 제안한다. 실험결과 제안한 버스 인코딩 기법은 완벽하게 crosstalk 지연를 제거한 반면, 기존의 다른 방법들에 비해 25% 이상 전력을 절약하였음을 보여준다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.745-753
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• 2016

This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180 nm process. The entire system consumes 8 nW in standby mode, and the bus achieves 17.5 pJ/bit/chip.

• 한국전자파학회논문지
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• 제13권10호
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• pp.1040-1047
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• 2002

본 논문에서는 인쇄회로기판을 기구물에 기계적으로 고정시키고, 전기적으로 접지시키기 위해 사용되는 스크류 연결이 파워버스 잡음에 미치는 영향을 분석하였다. 스크류는 인쇄회로기판과 기구물을 연결하기 위하여 파워버스를 관통하게 되며, 이는 파워버스 잡음에 영향을 미치게 된다. 이러한 스크류 연결의 효과를 확인하기 위하여 스크류가 없는 기판과 5개의 스크류를 사용하여 인쇄회로기판과 기구물의 간격을 0.5 mm로 설정한 경우를 비교하였다. 비교 결과 제안된 방법은 스크류가 없는 경우에 비해 0.1 GHz - l GHz의 주파수 대역에서 5 dB 이상 잡음 특성이 개선되는 것을 확인하였다. 또한 신호선이 존재하는 4층 인쇄회로기판에 스크류를 사용한 경우 600 MHz까지 신호의 특성이 개선되는 것을 확인하였다. 본 연구는 고속 회로 및 기구물 설계에 유용하게 활용될 수 있을 것으로 기대된다.

• Journal of Electrical Engineering and Technology
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• 제8권6호
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• pp.1305-1309
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• 2013

The application of the superconducting fault current limiter (SFCL) in a power distribution system is expected to contribute the voltage-sag suppression of the bus line as well as the fault-current reduction of the fault line. However, the application effects of the SFCL on the voltage sag of the bus line including the fault current are dependent on its application location in a power distribution system. In this paper, we investigated the fault current limiting and the voltage sag suppressing characteristics of the SFCL due to its application location such as the outgoing point of the feeder, the bus line, the neutral line and the 2nd side of the main transformer in a power distribution system, and analyzed the trace variations of the bus-voltage and fault-feeder current. The simulated power distribution system, which was composed of the universal power source, two transformers with the parallel connection and the impedance load banks connected with the 2nd side of the transformer through the power transmission lines, was constructed and the short-circuit tests for the constructed system were carried out. Through the analysis on the short-circuit tests for the simulated power distribution system with the SFCLs applied into its representative locations, the effects from the SFCL's application on the power distribution system were discussed from the viewpoints of both the suppression of the bus-voltage sag and the reduction of the fault current.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2005년도 종합학술발표회 논문집 Vol.15 No.1
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• pp.149-152
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• 2005

The DC power-bus' resonance is frequently attributed to EMI sources in the PCBs. Subsequently, it will ruin the digital signal integrity within one system or between adjacent systems in the form of conducted or radiated emission. Hence, since it is of importance to examine the PCB's emission, this paper sheds a light on the radiated emission from the power-bus with regards to its resonance modes. A full-wave analysis method is used to calculate the impedance and radiated electric fields and is validated by physics and an EM analysis tool.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(2)
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• pp.874-877
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• 2004

This paper presents the bus controller analysis of a power control unit of GEO satellite with 3kW power output. The sensing error of bus voltage produce control signal of the shunt switch assembly and the battery power converter, and the tolerance of error signal generated decide the stability of proposed system. The worst case analysis considered for the initial tolerance, temperature effect, tolerance of end of life is peformed to verify a designed bus controller. And also, the stability of system proposed according to moving of zero and pole values by some component failures is analyzed.

• Journal of Electrical Engineering and Technology
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• 제9권4호
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• pp.1202-1209
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• 2014

A novel integrated optimization method is proposed to combine both generation and transmission line expansion problem considering bus voltage limit. Most of the existing researches on the combined generation and transmission expansion planning cannot consider bus voltages and reactive power flow limits because they are mostly based on the DC power flow model. In this paper the AC power flow model and nonlinear constraints related to reactive power are simplified and modified to improve the computation time and convergence. The proposed method has been successfully applied to Garver's six-bus system which is one of the most frequently used small scale sample systems to verify the transmission expansion method.