• Proceedings of the KSR Conference
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• 2011.10a
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• pp.2348-2356
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• 2011

In recent years, many researches for DC power distributed system (PDS) are being preformed and the importance of the DC PDS is more and more emphasized. Furthermore, in the railway system, the DC PDS is used in subway station lighting, facilities, etc. In the DC PDS, DC bus voltage instability may be occurred by the operation of multiple parallel loads such as pulsed power load, motor drive system, and constant power loads. Thus, good quality and high reliability for electric power are required and voltage bus conditioner (VBC) may be used the DC PDS. The VBC is a DC/DC converter for mitigation of the bus transients. In this paper, adaptive controller is designed. The simulation results by PSIM are presented for validating the proposed control algorithm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.213-220
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• 2006

This paper investigates how the PCB power-bus sturcture's characteristics are influenced by the loading of decoupling capacitors in conjunction to other lumped elements including vias. The fields and impedance profiles are rigously evaluated and analyzed on various cases loaded with the above components and their effects will be given to bring better PCB EMC countermeasurs.

• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.76-85
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• 2016

This paper presents a method of decision on where bus splitting is needed to reduce fault current level of power systems and to satisfy the fault current constraints. The method employs a modified fault current constrained optimal power flow (FCC-OPF) with X variables for the candidate locations of splitting and for decision making on whether to split or not, it adopts soft-discretization by augmenting inversed U-shaped penalty terms. Also, this paper discusses the procedure on the adequate selection of bus splitting locations based on the results of the modified FCC-OPF, to reduce the total number of the actions taken.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.12B
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• pp.1548-1555
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• 2011

In ultra-deep submicron technology, minimization of propagation delay and power consumption on buses is one of the most important design objectives in system-on-chip (SOC) design. Crosstalk between adjacent wires on the bus may create a significant portion of propagation delay. Elimination or minimization of such faults is crucial to the performance and reliability of SOC designs. Most of the previous works on bus encoding are targeted either to minimize the bus switching or minimize the crosstalk delay, but not both. This paper proposes a new bus encoding scheme which can adaptively select one of functions "invert" and "logic-convert" according the number of bus switching on an encoded 4-bit cluster. This scheme leads to minimization of both crosstalk and bus switching. In experiment result, our proposed encoding technique consumes about 25% less power over the previous, while completely eliminating the crosstalk delay.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.745-753
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• 2016

This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180 nm process. The entire system consumes 8 nW in standby mode, and the bus achieves 17.5 pJ/bit/chip.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.10
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• pp.1040-1047
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• 2002

In this paper, we investigated noise decoupling on the power bus by the screw connection, used to the mechanical join and grounding of the PCB ground to chassis. The screw connection penetrates the power bus and then it affects noise propagation on the power bus. To verify effect of the screw connection, we compare bare board with board having screws connection with 0.5 mm separation between power bus and chassis. From these results, we observed that the power bus noise was decreased about 5 dB at the frequency range from 0.1 GHz to 1 GHz. Also, we verified that a 4-layer PCB with signal trace had the better signal quality up to 600 MHz by the screw connection. Therefore, these results will be useful in designing to the high speed circuit and chassis.

• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1305-1309
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• 2013

The application of the superconducting fault current limiter (SFCL) in a power distribution system is expected to contribute the voltage-sag suppression of the bus line as well as the fault-current reduction of the fault line. However, the application effects of the SFCL on the voltage sag of the bus line including the fault current are dependent on its application location in a power distribution system. In this paper, we investigated the fault current limiting and the voltage sag suppressing characteristics of the SFCL due to its application location such as the outgoing point of the feeder, the bus line, the neutral line and the 2nd side of the main transformer in a power distribution system, and analyzed the trace variations of the bus-voltage and fault-feeder current. The simulated power distribution system, which was composed of the universal power source, two transformers with the parallel connection and the impedance load banks connected with the 2nd side of the transformer through the power transmission lines, was constructed and the short-circuit tests for the constructed system were carried out. Through the analysis on the short-circuit tests for the simulated power distribution system with the SFCLs applied into its representative locations, the effects from the SFCL's application on the power distribution system were discussed from the viewpoints of both the suppression of the bus-voltage sag and the reduction of the fault current.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.149-152
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• 2005

The DC power-bus' resonance is frequently attributed to EMI sources in the PCBs. Subsequently, it will ruin the digital signal integrity within one system or between adjacent systems in the form of conducted or radiated emission. Hence, since it is of importance to examine the PCB's emission, this paper sheds a light on the radiated emission from the power-bus with regards to its resonance modes. A full-wave analysis method is used to calculate the impedance and radiated electric fields and is validated by physics and an EM analysis tool.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.874-877
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• 2004

This paper presents the bus controller analysis of a power control unit of GEO satellite with 3kW power output. The sensing error of bus voltage produce control signal of the shunt switch assembly and the battery power converter, and the tolerance of error signal generated decide the stability of proposed system. The worst case analysis considered for the initial tolerance, temperature effect, tolerance of end of life is peformed to verify a designed bus controller. And also, the stability of system proposed according to moving of zero and pole values by some component failures is analyzed.

• Journal of Electrical Engineering and Technology
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• v.9 no.4
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• pp.1202-1209
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• 2014

A novel integrated optimization method is proposed to combine both generation and transmission line expansion problem considering bus voltage limit. Most of the existing researches on the combined generation and transmission expansion planning cannot consider bus voltages and reactive power flow limits because they are mostly based on the DC power flow model. In this paper the AC power flow model and nonlinear constraints related to reactive power are simplified and modified to improve the computation time and convergence. The proposed method has been successfully applied to Garver's six-bus system which is one of the most frequently used small scale sample systems to verify the transmission expansion method.