• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.963-972
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• 2002

An 8192-point pipelined FFT/IFFT processor core is designed, which can be used in multi-carrier modulation systems such as DUf-based VDSL modem and OFDM-based DVB system. In order to improve the signal-to-quantization-noise ratio (SQNR) of FFT/IFFT results, two-step convergent block floating-point (TS_CBFP) scaling is employed. Since the proposed TS_CBFP scaling does not require additional buffer memory, it reduces memory as much as about 80% when compared with conventional CBFP methods, resulting in area-and power-efficient implementation. The SQNR of about 60-㏈ is achieved with 10-bit input, 14-bit internal data and twiddle factors, and 16-bit output. The core synthesized using 0.25-$\mu\textrm{m}$ CMOS library has about 76,300 gates, 390K bits RAM, and twiddle factor ROM of 39K bits. Simulation results show that it can safely operate up to 50-㎒ clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. It was verified by Xilinx FPGA implementation.

• Journal of the Optical Society of Korea
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• v.17 no.2
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• pp.188-199
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• 2013

This paper presents a novel algorithm for nighttime detection of the lane markers painted on a road at night. First of all, the proposed algorithm uses neighborhood average filtering, 8-directional Sobel operator and thresholding segmentation based on OTSU's to handle raw lane images taken from a digital CCD camera. Secondly, combining intensity map and gradient map, we analyze the distribution features of pixels on boundaries of lanes in the nighttime and construct 4 feature sets for these points, which are helpful to supply with sufficient data related to lane boundaries to detect lane markers much more robustly. Then, the searching method in multiple directions- horizontal, vertical and diagonal directions, is conducted to eliminate the noise points on lane boundaries. Adapted Hough transformation is utilized to obtain the feature parameters related to the lane edge. The proposed algorithm can not only significantly improve detection performance for the lane marker, but it requires less computational power. Finally, the algorithm is proved to be reliable and robust in lane detection in a nighttime scenario.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.213-216
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• 2004

This paper describes design and implementation of the 5.5 GHz VCO with parallel-branch inductors using 0.8${\mu}m$ SiGe HBT process technology. The proposed parallel-branch inductor shows $12 \%$ improvement in quality factor in comparison with the conventional inductor. A phase noise of -93 dBc/Hz is measured at 100 kHz offset frequency, and the harmonics in the VCO are suppressed less than -23 dBc. The single-sided output power of the VCO is -6.5$\pm$1.5 dBm. The manufactured VCO consumes 15.0 mA with 2.5 V supply voltage. Its chip areas are 1.8mm ${\times}$ 1.2mm.

• Transactions of the Korean Society of Automotive Engineers
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• v.24 no.2
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• pp.161-168
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• 2016

CNG engine has been used as a transportation because of higher thermal efficiency and lower CO2 and particulate matter. However its out put power is decreased due to cylinder-to-cylinder variation during the supply of air-fuel mixture to the each cylinder. It also causes noise and vibration. So in this study, 1D engine simulation model was validated by comparison with experiment data and 3D CFD simulation was conducted to steady-state flow analysis about each manifold geometry. Then, the effects of various intake manifold geometries on variation were evaluated by using 1D-3D coupling analysis at engine speed of 2100 rpm range in 12 L CNG engine. As a result, variation was improved about 4 % though 3D CFD analysis and there was a variation within 3 % using 1D-3D coupling analysis.

• 한국태양에너지학회:학술대회논문집
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• 2008.04a
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• pp.275-280
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• 2008

Photovoltaic(PV) permit the on-site production of electricity without concern for fuel supply or environmental adverse effects. The electrical power is produced without noise and little depletion of resources. So BIPV(Building-Integrated Photovoltaic) system have been increased around the world. Hereby the relative installation costs of the system will be relatively low compared to traditional installations of PV in high-rise buildings. This paper examined possibility of BIPV system of cold facade type and analyzed of performance of BIPV system of cold facade type. The system is influenced by conditions such as irradiation, module temperature, shade and architectural component etc. If this BIPV system of 1.1kW is possible the natural ventilation in the summer case, the temperature of PV module decrease and then the efficiency of PV system increase generally. By the results, the annual averaged PR of BIPV system of cold facade type is about 73.1%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.675-681
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• 2016

A 41dB gain control range $6^{th}$-order band-pass receiver front-end (RFE) using CMOS switched frequency translated impedance (FTI) is presented in a 40 nm CMOS technology. The RFE consists of a frequency tunable RF band-pass filter (BPF), IQ gm cells, and IQ TIAs. The RF BPF has wide gain control range preserving constant filter Q and pass band flatness due to proposed pre-distortion scheme. Also, the RF filter using CMOS switches in FTI blocks shows low clock leakage to signal nodes, and results in low common mode noise and stable operation. The baseband IQ signals are generated by combining baseband Gm cells which receives 8-phase signal outputs down-converted at last stage of FTIs in the RF BPF. The measured results of the RFE show 36.4 dB gain and 6.3 dB NF at maximum gain mode. The pass-band IIP3 and out-band IIP3@20 MHz offset are -10 dBm and +12.6 dBm at maximum gain mode, and +14 dBm and +20.5 dBm at minimum gain mode, respectively. With a 1.2 V power supply, the current consumption of the overall RFE is 40 mA at 500 MHz carrier frequency.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.499-504
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• 2017

A UHF CMOS variable gain low-noise amplifier (LNA) is designed for mobile digital TV tuners. The proposed LNA adopts a feedback topology to cover a wide frequency range from 474 to 868 MHz, and it supports the notch filter function for the interoperability with the GSM terminal. In order to handle harmonic distortion by strong interferers, the gain of the proposed LNA is step-controlled while keeping almost the same input impedance. The proposed LNA is implemented in a $0.11{\mu}m$ CMOS process and consumes 6 mA at a 1.5 V supply voltage. In the measurement, it shows the power gain of greater than 16 dB, NF of less than 1.7 dB, and IIP3 of greater than -1.7 dBm for the UHF band.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.60-68
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• 2000

This paper describes a design methodology for the CMOS current source which can be implemented in standard memory process. The proposed techniques provide a good characteristic against the power-supply variation by utilizing a self-bias circuit and the reduction of the first-order component of the temperature variation through the new temperature compensation technique and include a new current-sensing start-up circuit enabling a robust operation against the voltage noise generated during the operation of the chip. In addition to the circuit-design technology, techniques where the proposed CMOS current-reference circuit can be applied to the clocking circuits of a very high-speed DRAM are presented. The feasibility of the suggested design methodology for the CMOS current reference is demonstrated by both the analytical method and the circuit simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.198-206
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• 2013

This paper presents a wide band, fine-resolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 ${\mu}m$ digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 ${\mu}m$ process and the die area of the solenoid inductor is 0.013 $mm^2$. The DCO tuning range is about 54 % at 4.1 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The measured phase noise of the DCO output at 5.195 GHz is -110.61 dBc/Hz at 1 MHz offset.

• Journal of Ocean Engineering and Technology
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• v.16 no.1
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• pp.64-70
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• 2002

This paper shows the results of the development of a small size of digital type continuous and intermittent welding auto-carriage based on microprocessor (Intel 80196KC) for welding process with long welding line. The developed welding auto-carriage loads welding torch and tracks welding line. It is an automaton largely used for welding process with a lot of long welding lines such as shipbuilding and structure. Most traditional auto-carriages have been developed based on analog circuit for open loop control. So this analog circuit welding auto-carriage cannon control welding speed. Specially welding auto-carriage for intermittent welding condition is so complicated and has the low precision of control performance in welding distance and non-welding distance. The auto-carriage developed in this paper has the following characteristics: It has not only functions of traditional carriage but also functions such as pseudo-welding process of big iron structures, intermittent welding in order to limit heat for welding thin plates, crater treatment of the final step of welding, acceleration at the initial step of welding and deceleration in the final step of welding. The main control board of auto-carriage, power supply system and DC motor drive wee developed and manufactured. The welding speed and the welding distance of the developed auto-carriage are controlled accurately by feedback control using photo-sensor. Hardware and software robust against the heat and noise produced on the welding process are developed.