• Journal of Communications and Networks
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• v.16 no.3
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• pp.301-304
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• 2014

This paper proposes accurate interference probability and bit error rate formulas for cognitive relay networks with underlay spectrum sharing and channel estimation error (CEE). Numerous results reveal that the CEE not only degrades the performance of secondary systems (SSs) but also increases interference power caused by SSs to primary systems (PSs), eventually unfavorable to both systems. A solution to further protect PSs from this effect through reducing the power of secondary transmitters is investigated and analyzed.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2669-2671
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• 2000

In this paper, a new model error following sliding mode control is considered with a novel sliding surface for the error. This novel sliding surface has nominal dynamics of an original state of the error system and makes it possible that the Sliding Mode Control(SMC) technique for the error of the model following is used with the various types of controllers. Its design is based on the augmented system whose dynamics have a higher order than that of the original error system. The reaching phase is removed by using an initial virtual state which makes the initial error state sliding function equal to zero.

• Journal of the Ergonomics Society of Korea
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• v.19 no.1
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• pp.1-9
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• 2000

This study was performed to investigate some characteristics on human error proneness in the computerized work environment. Our concerning theme was on human error likelihood according to personal temperament. Two experiments were performed. The first experiment was to study the effect of field- independence/dependence on error likelihood. The second experiment was on error proneness. These experiments were performed in information search task. which was most frequent task in computerized work environment such as the control room of nuclear power plant. Ten subjects were participated in this study. Analyzed results are as follows. Field-independence/dependence had a significant effect in both information search time and error frequency. Error proneness had a significant effect in both factors, too. And, a positive correlation was found between error frequency and information search time. These results will be utilized as a basis to study operator's error proneness in the computerized control room of nuclear power plant. later on.

• Proceedings of the KIPE Conference
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• 2004.11a
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• pp.85-89
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• 2004

This paper presents Power Control and Distribution Unit development of GEO satellite with 3kW power output. The sensing error of bus voltage produce control signal of the shunt switch assembly and battery power converter, and the tolerance of error signals generated decide the stability of proposed system. The dynamic characteristics of main bus according to the load changing and the control logic of FPGA are simulated. In order to verify the proposed design, the simulation and experimental results for solar array shunt switch, battery power converter and bus controller are shown.

• Journal of IKEEE
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• v.14 no.2
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• pp.90-97
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• 2010

The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device and DTMOS Error Amplifier is presented in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS(DT-CMOS) with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an DT-CMOS error amplifier and a comparator circuit as a block. the proposed DT-CMOS Error Amplifier has 72dB DC gain and 83.5deg phase margin. also Error Amplifier that use DTMOS more than CMOS showed power consumption decrease of about 30%. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device is achieved the high efficiency near 96% at 100mA output current. And DC-DC converter is designed with Low Drop Out regulator(LDO regulator) in stand-by mode which fewer than 1mA for high efficiency.

• Journal of Korea Multimedia Society
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• v.20 no.7
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• pp.1046-1053
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• 2017

We propose a design method of high accuracy power measuring device and the method of securing the reliability of the measured data. As a design method for the development of the high accuracy power measuring device, the circuit was made by reflecting the high accuracy power measuring ICs and the CT (Current Transformer). To ensure the reliability of the power meter, we requested to the watt-hour meter certified testing organization to measure the error rate, and the error rate of active power based on the "Wattmeter Technical Standard(Revision notify 2014-283)" was measure, and the error rate was confirmed to be less than 0.1%.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.10
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• pp.1388-1394
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• 2018

In this paper, the improvement of the control response by using the error compensator to improve the stability of the control in the power conversion system is verified. Typically a closed loop control method is used to improve the control response characteristics in a traditional power conversion system and this is accomplished by generating a PWM waveform. In this paper, the newly constructed Type3 compensator to overcome the existing such as PI controller or Type2 compensator has been developed to improve the control stability of these closed loop control systems and the effectiveness of the use of error compensation devices was verified by presenting technique to improve stability and select its parameters by expanding the range of phase gains. Stability improvements are shown by the extension of the phase gain range and parameter selection techniques and the effects of using the error compensation device are verified accordingly.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.8
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• pp.1407-1413
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• 2000

This paper presents a feedforward linear power amplifier (LPA) using error feedback technique to achieve low intermodulation distortions(IMD) of power amplifiers for base stations. Especially, the proposed linear power amplifier is applied to feedforward technique combined with error feedback technique, which has no loss of amplifier gain unlike typical feedback technique. The proposed LPA is designed by using HP ADS ver. 1.3, fabricated. When two-tone signals at 1850 MHz and 1851.25 MHz with -7 dBm/tone from synthesizers are injected into the main power amplifier with gain of 28 dB and P1dB of 1W, the proposed LPA could reduce more than 35 dB.

• Journal of Korea Multimedia Society
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• v.25 no.10
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• pp.1448-1456
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• 2022

This paper studies a model to diagnose efficiency reduction of inverter using Multilayer Perceptron(MLP). In this study, two inverter data which started operation at different day was used. A Multilayer Perceptron model was made to predict photovoltaic power data of the latest inverter. As a result of the model's performance test, the Mean Absolute Percentage Error(MAPE) was 4.1034. The verified model was applied to one-year-old and two-year-old data after old inverter starting operation. The predictive power of one-year-old inverter was larger than the observed power by 724.9243 on average. And two-year-old inverter's predictive value was larger than the observed power by 836.4616 on average. The prediction error of two-year-old inverter rose 111.5572 on a year. This error is 0.4% of the total capacity. It was proved that the error is meaningful difference by t-test. The error is predicted value minus actual value. Which means that PV system actually generated less than prediction. Therefore, increasing error is decreasing conversion efficiency of inverter. Finally, conversion efficiency of the inverter decreased by 0.4% over a year using this model.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.236-239
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• 1999

This paper describes a low-power design of decimation filter. To reduce power consumption, an approximate processing method which controls the error in canonic signed digit(CSD) coefficients is proposed. The CSD representation reduces the number of operations by representing multiplications with add and shift operations. The proposed method further reduces the number of operations by controlling the error of CSD coefficient. Processor type architecture is used to implement the proposed method. Simulation result shows that the number of operations is reduced to 56%, 35% and 10% at each approximated filter level.