• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.227-230
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• 2001

This paper deals with a bidirectional ac-dc converter used in ups system application. We propose a Voltage-Source-Charge-Pump-Power-Factor-Correction(VS-CPPFC) ac-dc converters. First of all, we propose a charge pump power-factor-correction converter. Secondly, we derive and analyse a unity power factor condition. The proposed topology is based on a half-bridge for the primary and a current-fed push pull for the secondary side of a high frequency isolation transformer. The advantage of bidirectional flow of power achieved by using the same power components is that the circuit is simple and efficient. And the galvanically isolated topology is specially attractive in battery charge/discharge circuits in ups system. We design equivalent model for the steady-state circuit and analyse operation waveforms for each mode. We show that the proposed model can be applied to ups system by simulation processes.

• Journal of Electrical Engineering and Technology
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• 제8권4호
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• pp.951-958
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• 2013

This paper proposes the controller design for a stability improvement of an on-board battery charger. The system is comprised of a power factor correction (PFC) circuit and phase shift full-bridge DC-DC converter. The PFC circuit performs the control of the DC-link voltage and the input power factor. The DC-DC converter regulates the voltage and the current in the battery using the DC-link voltage. This paper proposes the design method of PI controller for the PFC circuit using a small signal model. The analysis and design of a type-three controller for the DC-DC converter is also presented. A simulation and experiment has been performed on the on-board battery charger and their results are presented to verify the validity of the proposed system.

• 전력전자학회논문지
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• 제22권6호
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• pp.469-475
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• 2017

Using impedance matching techniques as a way to increase system power transferability in capacitive wireless power transmission has been widely investigated in conventional studies. However, these techniques tend to increase the circuit volume and thus counterbalance the advantage of the simplicity in the energy link structure. In this paper, a compact circuit topology with one leakage-enhanced transformer is proposed in order to minimize the circuit volume for the capacitive power transfer system. This topology achieves a reactive compensation, and the system quality factor value can be reduced by the turn ratio. As a result, this topology not only reduces the overall system volume but also minimizes the voltage stress of the link capacitor. An optimal design guideline for the leakage-enhanced transformer is also presented. The advantages of the proposed scheme over the conventional method in terms of power efficiency and circuit volume are revealed through an analytic comparison. The feasibility of applying the new topology is also verified by conducting 50 W hardware tests.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2002년도 춘계학술대회 논문집
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• pp.735-739
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• 2002

PTB(Power Transfer Breaker) is a device which incorporate the functions of ACB(Air Circuit Breaker) and ATS(Automatic Transfer Switch). ACB is a circuit breaker against overload and ATS is a switching device to transfer the load between two electric power sources. An existing PTB design based upon the 5 bar & cam mechanism has been regarded to be too complex and thus a simpler 4 bar mechanism with trigger lock is proposed. Experimentation and optimization of the trigger lock is presented.

• 전기전자학회논문지
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• 제12권4호
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• pp.211-216
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• 2008

이 논문은 MOS 전류모드 논리 (MOS current-mode logic circuit, MCML) 회로를 이용하여 저 전력 특성을 갖는 8${\times}$8 비트 병렬 곱셈기를 설계하였다. 설계한 곱셈기는 회로가 동작 하지 않을 때의 정적 전류의 소모를 최소화하기 위하여 슬립 트랜지스터 (sleep-transistor)를 이용하여 저 전력 MOS 전류모드 논리회로를 구현하였다. 설계한 곱셈기는 기존 MOS 전류모드 논리회로에 비해 대기전력소모가 1/50으로 감소하였다. 또한, 이 회로는 기존 MOS 전류모드 논리회로에 비해 전력소모에서 10.5% 감소하였으며, 전력소모와 지연시간의 곱에서 11.6%의 성능 향상이 있었다. 이 회로는 삼성 0.35${\mu}m$ 표준 CMOS 공정을 이용하여 설계하였으며, HSPICE를 통하여 검증하였다.

• 전력전자학회논문지
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• 제18권5호
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• pp.458-465
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• 2013

This paper proposes a novel soft-switched auxiliary resonant circuit to provide a Zero-Voltage-Transition at turn-on for a conventional PWM boost converter in a PFC application. The proposed auxiliary circuit enables a main switch of the boost converter to turn on under a zero voltage switching condition and simultaneously achieves both soft-switched turn-on and turn-off. Moreover, for the purpose of an intelligent multi-chip power module fabrication, the proposed circuit is designed to satisfy several design constraints including space saving, low cost, and easy fabrication. As a result, the circuit is easily realized by a low rated MOSFET and a small inductor. Detail operation and the circuit waveform are theoretically explained and then simulation and experimental results are provided based on a 1.8 kW prototype PFC converter in order to verify the effectiveness of the proposed circuit.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 C
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• pp.1220-1223
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• 1998

High Power Laboratory is the facility for building to simulate the various phenomena generated from electric systems of the real world and to test making and breaking capability, switching capability and durability of circuit breaker, switchgear and other electric utilities, moreover, load equipments which contain capacitor bank is installed for studying the diverse effects originated from the constituent of load through entire systems or receiving end. Such factors, abnormal voltage or current, can be serious in electrical systems, especially, in the case caused by capacitive components such as overvoltage or inrushcurrent, the problems may be more fatal to the systems. In this paper, the optimal design of capacitor bank which will be equipped in High Power Laboratory, which is for simulating as closely as the practical phenomena resulted from the capacitive currents, and the verification aided by computer simulations are presented. For this, analysis of the circuit characteristics according to the standards which can be criteria of the capacitive current tests and the test circuit configuration in accordance with the analysis are proposed in prelude. In the body of the paper the optimal design of capacitor bank has been obtained on the basis of all conditions mentioned above and the test circuit configuration with LGIS test requirements. furthermore, analysis and verification for the design are derived by EMTP. finally, evaluation for the capacitor bank design and further study plan are concluded.

• 한국정보통신학회논문지
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• 제15권11호
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• pp.2457-2464
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• 2011

본 논문에서는 압전 소자를 이용한 진동에너지 하베스팅 회로를 설계하였다. 압전소자의 전력-전압 특성을 이용하여 최대 전력을 부하로 전달하기 위한 MPPT(Maximum Power Point Tracking) 제어 기능을 구현하였다. MPPT 제어 회로는 압전소자의 출력 단에 연결된 전파 정류회로의 개방회로 전압을 주기적으로 샘플링하여 최대 가용전력이 생성되는 지점을 추적하고 이를 부하로 전달하는 역할을 한다. 제안된 진동에너지 하베스팅 회로는 $0.18{\mu}m$ CMOS 공정으로 설계하였다. 모의실험 결과 설계된 회로의 최대 전력 효율은 91%이고, pad를 제외한 칩 면적은 $700{\mu}m{\times}730{\mu}m$이다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.1301-1304
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• 2005

본 논문에서는 전력선 통신 시스템에서 급격하게 변화는 임피던스 때문에 발생하는 에러율을 개선하기 위하여 제안한 D급 증폭 구동 회로를 적용하였다. 전력선 모뎀에, 일반적인 구동회로인 전압 구동 회로와 전류 구동 회로를 제작하여 실험을 하였다. 그리고 같은 전력선 모뎀에 본 논문에서 제안한 D급 증폭 회로를 이용한 구동 회로를 사용하여 실험을 하였다. 실험 결과 본 논문에서 설계한 구동 회로가 전력선 통신에서 임피던스 변화에 대하여 다른 구동 회로보다 성능이 우수함을 보였다.

• 전력전자학회논문지
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• 제25권5호
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• pp.412-419
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• 2020

In this study, a 70 W buck converter using GaN metal-oxide-semiconductor field-effect transistor (MOSFET) is developed. This converter exhibits over 97 % efficiency, high power density, and 48 V-to-12 V/1.2 V/1 V (triple output). Three gate drivers and six GaN MOSFETs are placed in a 1 ㎠ area to enhance power density and heat dissipation capacity. The theoretical switching and conduction losses of the GaN MOSFETs are calculated. Inductances, capacitances, and resistances for the output filters of the three buck converters are determined to achieve the desired current, voltage ripples, and efficiency. An equivalent circuit model for the thermal analysis of the proposed triple-output buck converter is presented. The junction temperatures of the GaN MOSFETs are estimated using the thermal model. Circuit operation and temperature analysis are evaluated using a circuit simulation tool and the finite element analysis results. An experimental test bed is built to evaluate the proposed design. The estimated switch and heat sink temperatures coincide well with the measured results. The designed buck converter has 130 W/in³ power density and 97.6 % efficiency.