• Title/Summary/Keyword: Power Threshold

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Soliton coupler using a bent nonlinear waveguide (굽은 비선형 도파로를 이용한 솔리톤 결합기)

  • 정준영;강병한;정제명
    • Korean Journal of Optics and Photonics
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    • v.10 no.6
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    • pp.487-493
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    • 1999
  • In this paper, we studied the characteristics of a soliton coupler using a bent nonlinear waveguide. The bent soliton coupler has very ,harp switching characteristic like the conventional soliton coupler due to the threshold effect of soliton emi,sion from the nonlinear waveguide. By using the bent structure, we can reduce the threshold power for the soliton emission. We consider the saturation effect of nonlinearity and the loss in the medium for more accurate and practical numerical analysis in wave propagation through the bent soliton coupler. The simulation results show that the consideration of the saturation effect and the ]os~ may be very important in the analyses and design of the nonlinear waveguide devices. The bent structure is useful for the emission of the spatial soliton with the low threshold power, when we consider the saturation and the loss effect. ffect.

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A Study on Fatigue Crack Propagation Threshold Characteristics in SA516/70 Steel at Low Temperature (SA516/70강의 저온피로크랙 전파 하한계특성에 관한 연구)

  • Park, K.D.;Kim, J.H.;Park, H.D.;Choi, B.K.
    • Journal of Power System Engineering
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    • v.4 no.4
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    • pp.41-47
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    • 2000
  • Fatigue crack propagation rate and threshold characteristics of the SA516/70 steel which is used for the low temperature pressure vessels, were studied in the room temperature of $25^{\circ}C$ and low temperature ranges of $-10^{\circ}C,\;-30^{\circ}C,\;-60^{\circ}C\;and\;-80^{\circ}C$ with stress ratio of R=0.1. In the logarithmic relationship between the fatigue crack propagation rate($d{\alpha}/dN$) and stress intensity factor range ${\Delta}K$, the linear relationship was obtained up to $d{\alpha}/dN=4.425{\times}10^4mm/cycle$ in the same of room temperature, but in low temperature case, the relationship was extended to the range of low crack propagation rate. The fractured specimens were examined by SEM. Tested results showed that specimen failed at low temperature exhibit the quasi-cleavage fracture formation however considerable ductility proceed final fracture.

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Sensor Fault Detection, Localization, and System Reconfiguration with a Sliding Mode Observer and Adaptive Threshold of PMSM

  • Abderrezak, Aibeche;Madjid, Kidouche
    • Journal of Power Electronics
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    • v.16 no.3
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    • pp.1012-1024
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    • 2016
  • This study deals with an on-line software fault detection, localization, and system reconfiguration method for electrical system drives composed of three-phase AC/DC/AC converters and three-phase permanent magnet synchronous machine (PMSM) drives. Current sensor failure (outage), speed/position sensor loss (disconnection), and damaged DC-link voltage sensor are considered faults. The occurrence of these faults in PMSM drive systems degrades system performance and affects the safety, maintenance, and service continuity of the electrical system drives. The proposed method is based on the monitoring signals of "abc" currents, DC-link voltage, and rotor speed/position using a measurement chain. The listed signals are analyzed and evaluated with the generated residuals and threshold values obtained from a Sliding Mode Current-Speed-DC-link Voltage Observer (SMCSVO) to acquire an on-line fault decision. The novelty of the method is the faults diagnosis algorithm that combines the use of SMCSVO and adaptive thresholds; thus, the number of false alarms is reduced, and the reliability and robustness of the fault detection system are guaranteed. Furthermore, the proposed algorithm's performance is experimentally analyzed and tested in real time using a dSPACE DS 1104 digital signal processor board.

Wear Leveling Technique using Bit Array and Bit Set Threshold for Flash Memory

  • Kim, Seon Hwan;Kwak, Jong Wook;Park, Chang-Hyeon
    • Journal of the Korea Society of Computer and Information
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    • v.20 no.11
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    • pp.1-8
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    • 2015
  • Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

Analysis of Switch Device Losses through Threshold Voltage and Miller Plateau Voltage (문턱전압과 밀러플래토 전압을 통한 스위치 소자의 손실 분석)

  • Park, Sae Hee;Seong, Ho-Jae;Hyun, Seung-Wook;Won, Chung-Yuen
    • Proceedings of the KIPE Conference
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    • 2017.11a
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    • pp.133-134
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    • 2017
  • This paper analyzes switch Device losses and efficiency depending on SiC and Si devices. The switch devices loss is compared to Si and SiC-based elements through Threshold Voltage and Miller Platequ Voltage. And analyzed through comparison of each switching loss by experiment.

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Efficient Low-Power Turbo Decoder (효율적인 저전력 터보 복호기)

  • 배성일;김재석
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.73-76
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    • 1999
  • In this paper, we propose a new design of turbo decoder. It contains the simple additional unit which automatically decides the number of the iteration by detecting of the reliability value as threshold value. We investigate the relationship between the reliability value and the number of the iteration. We find the optimal threshold value without noticeable loss in performance. As a results of the simulation, it reduces the average number of the iteration compared with the conventional turbo decoder.

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Effects of Noise Power Uncertainty on Energy Detection for Spectrum Sensing (잡음 전력의 불확실성이 에너지 검파 기반의 스펙트럼 감지에 미치는 영향)

  • Lim, Chang-Heon
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.48 no.11
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    • pp.22-27
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    • 2011
  • In spectrum sensing, an energy detector compares the energy of a received signal with a predetermined detection threshold and decides whether a primary user is active or not in a licensed frequency band. Here the detection threshold is related to the noise power level in the band. Most previous works on energy detection have assumed that the noise power is exactly known a priori. However, this assumption does not hold in practice since there may be some uncertainty about the noise power. So it is necessary to investigate its effects on the performance of energy detection for spectrum sensing. In this paper, we analyze the effects using the residue theorem for contour integral and present the associated numerical results.

A design of low power structures of texture caches for mobile 3D graphics accelerator (모바일 3D 그래픽 가속기를 위한 저전력 텍스쳐 캐쉬 구조 설계)

  • Kim, Young-Sik;Lee, Jae-Young
    • Journal of Korea Game Society
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    • v.6 no.4
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    • pp.63-70
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    • 2006
  • This paper studied various low power structures of texture caches for mobile 3D graphics accelerator to reduce the memory latency of texture data. Also the paper designed the texture cache with the variable threshold values of power mode transition according to the filtering algorithms. In the trace driven simulation, we compared the performance of those structures using Quake game engine as the benchmark. Also the algorithm was proposed and verified by the simulation, which has variable threshold values of power mode transitions according to the selected texture filtering method.

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Structure of Low-Power MOS Current-Mode Logic Circuit with Sleep-Transistor (슬립 트랜지스터를 이용한 저 전력 MOS 전류모드 논리회로 구조)

  • Kim, Jeong-Beom
    • The KIPS Transactions:PartA
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    • v.15A no.2
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    • pp.69-74
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    • 2008
  • This paper proposes a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The $16\;{\times}\;16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. This circuit is designed with Samsung $0.35\;{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.