• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.5
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• pp.2003-2021
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• 2020

Today's computer systems are widely integrated with CPU and GPU to achieve considerable performance, but energy consumption of such system directly affects operational cost, maintainability and environmental problem, which has been aroused wide concern by researchers, computer architects, and developers. To cope with energy problem, we propose a task-scheduling framework to reduce energy under performance constraint by rationally allocating the tasks across the CPU and GPU. The framework first collects the estimated energy consumption of programs and performance information. Next, we use above information to formalize the scheduling problem as the 0-1 knapsack problem. Then, we elaborate our experiment on typical platform to verify proposed scheduling framework. The experimental results show that our proposed algorithm saves 14.97% energy compared with that of the time-oriented policy and yields 37.23% performance improvement than that of energy-oriented scheme on average.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.3
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• pp.235-244
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• 2014

This article introduces recent trends in RHC (Receding Horizon Control), also known as MPC (Model Predictive Control), that has been well recognized in industry and academy as a systematic approach for optimal design and constraint management. Constrained and robust RHCs will be briefly reviewed with milestone results. Among the diverse developments and achievements of RHCs, implementation issues will be focused on, together with the latest applications. In particular, this article introduces results on how to solve a finite horizon open-loop optimal control problem in an efficient way, together with code generation for real-time execution and easy implementation. Instead of traditional applications such as refineries and petrochemical plants, this article highlights some selected emerging applications, such as energy management systems and mechatronics, that have resulted from state-of-the-art high performance computing power and advanced numerical schemes.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.548-552
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• 1987

The constraint condition of the loop filter is persented for the convergence of the random jitter accumulation fo the 2-nd order PLL (phase-locked loop) circuit used in digital regenerative repeater. This condition is confirmed under the assumption that the number of repeater chain is 5, bandwidth is 100. 0KHz, the power spectral density of white Gaussian noise is 1.0x10**-6 [W/Hz]. Also, it is shown that if the condition is satisfied, the accumulated random jitter and the alignment jitter will have the saturation characteristics.

• ETRI Journal
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• v.41 no.5
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• pp.619-625
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• 2019

In this paper, we propose an array pattern synthesis scheme using semidefinite programming (SDP) under array excitation power constraints. When an array pattern synthesis problem is formulated as an SDP problem, it is known that an additional rank-one constraint is generated inevitably and relaxed via semidefinite relaxation. If the solution to the relaxed SDP problem is not of rank one, then conventional SDP-based array pattern synthesis approaches fail to obtain optimal solutions because the additional rank-one constraint is not handled appropriately. To overcome this drawback, we adopted a bisection technique combined with a penalty function method. Numerical applications are presented to demonstrate the validity of the proposed scheme.

• 전기의세계
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• v.25 no.6
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• pp.81-88
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• 1976

The present voltage-reactive power control aims at an overall coordination of reactive power sources and voltage regulation devices to keep the bus voltages within their allowable bounds on one hand and to reduce the transmission losses on the other. This paper presents an efficient computer control scheme for the real-time control of system voltage and reactive power on the basis of a simplified linear equation by using the system characteristic constant. Computational algorithm is used for the minimization of bus voltage deviation in the first phase of optimization and for the reduction of transmission losses under the constraint of vlotage settling condition in the second phase. The numerical example for sample practical system is also given. The present study on the computer control scheme will contribute to the automation of power system operation in the near future.

• Journal of Electrical Engineering and Technology
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• v.9 no.1
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• pp.80-89
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• 2014

A stochastic optimal power flow (S-OPF) model considering uncertainties of load and wind power is developed based on chance constrained programming (CCP). The difficulties in solving the model are the nonlinearity and probabilistic constraints. In this paper, a limit relaxation approach and an iterative learning control (ILC) method are implemented to solve the S-OPF model indirectly. The limit relaxation approach narrows the solution space by introducing regulatory factors, according to the relationship between the constraint equations and the optimization variables. The regulatory factors are designed by ILC method to ensure the optimality of final solution under a predefined confidence level. The optimization algorithm for S-OPF is completed based on the combination of limit relaxation and ILC and tested on the IEEE 14-bus system.

• Management Science and Financial Engineering
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• v.19 no.1
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• pp.43-47
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• 2013

We investigate the effect of bank's market power on financing constraints of non-financial firms in 11 Asian countries between 1995 and 2009. Using firm-level data we analyze financial constraints with the Euler equation derived from the dynamic investment model. We find that with a highly concentrated banking sector firms which have high market power are less financially constrained. These results are consistent with an information-based hypothesis that more market power increases bank's advantage to produce information on potential borrowers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.1
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• pp.16-22
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• 2015

This paper proposes a power allocation method for multiple node beamforming with uniform circular array antennas to increase SIR of nodes in wireless mesh network. The proposed method calculates beamforming power allocation vectors that maximizes SIR satisfied with power constraint of HPA. The simulation results demonstrate the proposed method achieves the enhanced SIR of nodes than that of beamforming method.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.772-776
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• 2004

This paper proposes an interference avoidance approach for Constraint-Based Routing (CBR) algorithm in the Multi-Protocol Label Switching (MPLS) network. The MPLS network itself has a capability of integrating among any layer-3 protocols and any layer-2 protocols of the OSI model. It is based on the label switching technology, which is fast and flexible switching technique using pre-defined Label Switching Paths (LSPs). The MPLS network is a solution for the Traffic Engineering(TE), Quality of Service (QoS), Virtual Private Network (VPN), and Constraint-Based Routing (CBR) issues. According to the MPLS CBR, routing performance requirements are capability for on-line routing, high network throughput, high network utilization, high network scalability, fast rerouting performance, low percentage of call-setup request blocking, and low calculation complexity. There are many previously proposed algorithms such as minimum hop (MH) algorithm, widest shortest path (WSP) algorithm, and minimum interference routing algorithm (MIRA). The MIRA algorithm is currently seemed to be the best solution for the MPLS routing problem in case of selecting a path with minimum interference level. It achieves lower call-setup request blocking, lower interference level, higher network utilization and higher network throughput. However, it suffers from routing calculation complexity which makes it difficult to real task implementation. In this paper, there are three objectives for routing algorithm design, which are minimizing interference levels with other source-destination node pairs, minimizing resource usage by selecting a minimum hop path first, and reducing calculation complexity. The proposed CBR algorithm is based on power factor calculation of total amount of possible path per link and the residual bandwidth in the network. A path with high power factor should be considered as minimum interference path and should be selected for path setup. With the proposed algorithm, all of the three objectives are attained and the approach of selection of a high power factor path could minimize interference level among all source-destination node pairs. The approach of selection of a shortest path from many equal power factor paths approach could minimize the usage of network resource. Then the network has higher resource reservation for future call-setup request. Moreover, the calculation of possible path per link (or interference level indicator) is run only whenever the network topology has been changed. Hence, this approach could reduce routing calculation complexity. The simulation results show that the proposed algorithm has good performance over high network utilization, low call-setup blocking percentage and low routing computation complexity.

• The Magazine of the IEIE
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• v.25 no.5
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• pp.31-41
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• 1998

With the advent of portable electronic systems, power consumption has recently become a major issue in circuit and system design. Furthermore, the sophisticated fabrication technology makes it possible to embed more functions and features in a VLSI chip, consequently calling for both higher performance and lower power to deal with the ever growing complexity of system algorithms than in the past. VLSI designers should cope with two conflicting constraints, high performance and low power, offering an optimum trade off of these constraints to meet requirements of system. Historically, VLSI designers have focused on performance improvement, and power dissipation was not a design criteria but an afterthought. This design paradigm should be changed, as power is emerging as the most critical design constraint. In VLSI design, low power design can be accomplished through many ways, for instance, process, circuit/logic design, architectural design, and etc.. In this paper, a few low power design examples, which have been used in 8 bit micro-controller core, and can be used also in 4/16/32 bit micro-controller cores, are presented in the areas of circuit, logic and architectural design. We first propose a low power guidelines for micro-controller design in SAMSUNG, and more detailed design examples are followed applying 4 specific design guidelines. The 1st example shows the power reduction through reduction of number of state clocks per instruction. The 2nd example realized the power reduction by applying RISC(Reduced Instruction Set Computer) concept. The 3rd example is to optimize the algorithm for ALU(Arithmetic Logic Unit) to lower the power consumption, Lastly, circuit cells designed for low power are described.