• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.312-314
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• 2009

We have fabricated pentacene based organic thin film transistors (OTFTs) with formulated poly[4-vinylphenol] (PVP) gate dielectrics. The gate dielectrics is composed of PVP, poly[melamine-coformaldehyde] (PMF) and photo-initiator [1-phenyl-2-hydroxy-2-methylpropane-1-one, Darocur1173]. By adding small amount (1 %) of photo-initiator, the cross-linking temperature is lowered to $115^{\circ}C$, which is lower than general thermal curing reaction temperature of cross-linked PVP (> $180^{\circ}C$). The hysteresis and the leakage current of the OTFTs are also decreased by adding the PMF and the photoinitiator in PVP gate dielectrics.

• Journal of Information Display
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• v.9 no.2
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• pp.1-4
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• 2008

In this study, we investigate the capacitance-voltage (C-V) characteristics of metal-insulator-semiconductor (MIS) capacitors consisting of pentacene, as an organic semiconductor, and polymeric insulators such as poly(4-vinylphenol) (PVP) orpolystyrene (PS) prepared by spin-coating process, to analyze the interfacial characteristics between pentacene and polymeric insulators. Compared with the device with PS, the MIS capacitor with PVP exhibited a pronounced shift in the flat-band voltage according to the bias sweep direction. This hysteric feature in the C-V characteristics is thought to be attributed to the trapped charges at the interface between pentacene and PVP owing to the hydrophilicity of PVP. From the experimental results, we can conclude that surface polarity of polymeric insulator has a critical effect on the interfacial properties, thereby affecting the bias stability of organic thin-film transistors.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.30.2-30.2
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• 2009

본 연구에서는 stamping법을이용하여 절연막에 실리콘 나노와이어를 embed시킨 field-effect transistor(FET) 소자의 전기적 특성에 대하여 분석하였다. Stamping법은 나노와이어를 이용한 소자를 제작하는데 있어 쉽고 경제적인 방법으로 최근 많이 사용되고 있는데, 이 방법을 이용하여 나노와이어를 절연막에 embed 시켰다. 이때, 사용한 실리콘 나노와이어는 무전해 식각법을 통하여 합성하였다. 식각 시간을 조절하여 나노와이어의 길이가 $100{\mu}m$ 정도가 되도록 하였고, 나노와이어의 지름은 정제를 통하여 20 ~ 200nm내로 조절하였다. FET 소자의 게이트 절연막은가장 일반적으로 사용되는 SiO2 (200nm)와 고분자 절연막으로 잘 알려진 poly-4-vinylphenol(PVP)를 사용하였다. 실리콘 나노와이어의 전기적 특성을 각각 SiO2무기 절연막에서의 non-embedded상태, PVP 유기 절연막에서의 embedded 상태에서 비교분석 하였다. 전기적 특성은 I-V 측정을 통하여 Ion/Ioff ratio, 이동도, subthreshold swing, threshold voltage값을 평가하였다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.22.2-22.2
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• 2011

Si 나노와이어를 합성하는 다양한 방법들 중에서 Si 기판을 나노와이어 형태로 제작하는 무전해 식각법은 쉽고 간단하기 때문에 최근 많은 연구가 진행되고 있다. 무전해 식각법을 이용한 Si 나노와이어는 p 또는 n형의 전기적 특성을 갖는 Si 기판의 도핑농도에 따라 원하는 전기적 특성을 갖는 나노와이어를 얻을 수 있을 것이라는 기대가 있었지만 n형으로 제작된 나노와이어의 경우 식각에 의한 표면의 거칠기 때문에 그 특성을 나타내지 못하는 문제점을 가지고 있다. 본 연구에서는 무전해 식각법을 이용하여 p와 n형 나노와이어를 합성하고 field-effect transistors (FETs) 소자를 제작하여 각각의 특성을 구현하였다. 나노와이어와 절연막 사이의 계면 결함을 최소화하기 위하여 poly-4-vinylphenol (PVP) 고분자 절연막에 나노와이어를 삽입시킨 형태로 소자를 제작하였고, 특히 n형 나노와이어의 표면을 보다 평평하게 하기 위하여 열처리를 진행 하였다. 이렇게 각각의 특성이 구현된 나노와이어를 이용하여 soft-lithography 공정을 통해 complementary metal-oxide semiconductor (CMOS) 구조의 인버터 소자를 제작하였으며 그 전기적 특성을 평가하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1135-1138
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• 2006

By ink-jet printing method, organic thin-film transistors (OTFTs) having soluble 6,13-bis (triisopropylsilylethynyl) pentacene (TIPS pentacene) as an active material were fabricated. The TIPS pentacene solution was made with chlorobenzene and anisole. The solutions were printed on poly (4-vinylphenol) (PVP) dielectric layers and source/drain electrodes by piezo-type heads for bottom contact OTFTs. The dielectric layers had untreated or HMDS-treated conditions. The chlorobenzene device showed the highest field effect mobility of $0.016\;cm^2/Vs$ and the anisole HMDS-treated device shows the highest $I_{on}/I_{off}$ ratio of $10^5$.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.79.1-79.1
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• 2012

Si 기판을 무전해 식각하여 나노와이어 형태로 합성하는 방법은 쉽고 간단하기 때문에 이를 이용한 소자 특성 연구가 많이 진행되고 있다. 하지만 이러한 방법으로 제작된 Si 나노와이어의 경우 식각에 의하여 나노와이어 표면이 매우 거칠어지기 때문에 고유의 특성을 나타내기 어려워 표면 특성을 제어 할 수 있는 연구의 필요성이 대두되고 있다. 본 연구에서는 무전해 식각법을 이용하여 p와 n형 나노와이어를 각각 합성하고 그 특성을 구현하기 위하여 표면조절을 진행하였다. 특히 n형 나노와이어의 경우 표면의 OH- 이온으로 인하여 n채널 특성이 제대로 나타나지 않기 때문에 열처리를 이용하여 표면을 보다 평평한 형태로 조절하여 향상된 전기적 특성을 얻을 수 있었다. 여기에 나노와이어와 절연막 사이의 계면 결함을 최소화 하기 위하여 poly-4-vinylphenol (PVP) 고분자 절연막에 나노와이어를 삽입시켜 나노와이어의 문턱전압 값을 조절하였다. 이를 바탕으로 complementary metal-oxide semiconductor(CMOS) 구조의 인버터 소자를 제작하였으며 p형 나노와이어가 절연막에 삽입된 정도에 따라 인버터의 midpoint voltage 값을 조절 할 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.634-634
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• 2013

Transfer molding methods have a problem that weak adhesion between nanostructures and substrates. It is important to make various nano scale applications, also the stability of nanostructure on substrate is related with device performance. We studied an effect of poly 4-vinylphenol (PVP) as the polymeric adhesion layer between organic nanowires and a Si substrate when the nanowires are transferred by liquid-bridge-mediated nanotransfer molding method (LB-nTM). Their structural stability was examined by optical microscopy, scanning electron microscopy as multiple transfer molding and washing process. Field-effect transistors were fabricated with organic semiconductor nanowires on a polymeric adhesion layer and their electrical properties showed no significant difference as the one without the adhesion layer. As a result, adhesion layer can be used in the washing process and making multi-layer nano-scale patterns.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.937-939
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• 2009

In this paper, we report electrical properties of OTFTs made by ink-jet printing with polyvinylphenol (PVP) for bank layer and bis(triisopropylsilylenthynyl) pentacene (TIPS-pentacene) for semiconductor. We could achieve better crystallization and surface uniformity of TIPS pentacene by employing PVP bank layer. The OTFT with PVP bank layer exhibited an field-effect mobility of 0.18 $cm^2$/Vs, current on/off ratio of $2.09{\times}10^5$, and subthreshold slope of 0.42 V/decane.

• Clean Technology
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• v.19 no.4
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• pp.410-415
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• 2013

The supercapacitors were fabricated using silver (Ag) nano paste and activated carbon paste on the polyimide (PI) film and 5% potassium polyacrylate (PAAK) was used for gel electrolyte. In this paper, the current collector film and the electrode film were fabricated using screen printing. The thickness of printed silver paste was $7.3{\mu}m$ and the sheet resistance has the range of $5-7m{\Omega}/square$. An activated carbon with a surface area of $1,968m^2/g$, an electronic conducting agent (SUPER P, TIMCAL) and poly (4-vinylphenol) were mixed in 2-(2-buthoxyethoxy) ethyl acetate (BCA) with a ratio of 7:1:3 to fabricate the electrode paste. To analyze electrochemical characteristics, cyclic voltammetry was performed to evaluate the stability of the devices under the voltage range of -0.5-0.5 V. The calculated specific capacitances were 44.04 and 8.62 F/g for 10 and 500 mV/s scan rates, respectively.

• Journal of the Korean Applied Science and Technology
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• v.29 no.2
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• pp.199-204
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• 2012

Organic thin-film transistors (OTFTs) have received considerable attention because their potential applications for nano-scale thin-film structures have been widely researched for large-scale integration industries, such as semiconductors and displays. However, research in developing n-type materials and devices has been relatively shortage than developing p-type materials. Therefore, we report on the fabrication of top-contact [6,6]-phenyl-C61-butyricacidmethylester (PCBM) TFTs by using three different solvent, o-dichlorobenzene, toluene and chloroform. An appropriate choice of solvent shows that the electrical characteristics of PCBM TFTs can be improved. Moreover, our PCBM TFTs with the cross-linked Poly(4-vinylphenol) dielectric layer exhibits the most pronounced improvements in terms of the field-effect mobility (${\sim}0.034cm^2/Vs$) and the on/off current ratio (${\sim}1.3{\times}10^5$) for our results. From these results, it can be concluded that solvent-modification of an organic semiconductor in PCBM TFTs is useful and can be extended to further investigations on the PCBM TFTs having polymeric gate dielectrics. It is expected that process optimizations using solution-processing of organic semiconductor materials will allow the development of the n-type organic TFTs for low-cost electronics and various electronic applications.