• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05c
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• pp.55-58
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• 2001

In this paper, we present the results of the design and fabrication of the VCO(Voltage controlled Oscillator) using RF circuit simulator GENESYS and electromagnetic field simulator EMpower Frequency range is fabricated VCO is 850 MHz ~ 950 MHz, which is used Colpitts Circuit. the fabricated VCO is consisted of resonator, oscillator and MSL(Microstrip Line) is used in LC tuning circuit.(operated by negative feedback) MSL(Microstrip Line), Varactor(Plastic package), low noise TR(SOT-23), chip inductor(1608), chip capacitor(1005), chip resistance(1005). 1005 type is used for sample fabrication of VCO. In the fabrication process, circuit pattern is screen printed on the alumina substrates of over 99.9% purity. Center frequency of the sample VCO is 850MHz at $V_T=1.5V$, while the simulated value was 1.0GHz at $V_T=1.5V$. Variable frequency range of the sample is 860~950MHz in contrast to the 1068~1100MHz of the simulated values.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05c
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• pp.153-156
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• 2001

In this paper, we present the results of the design and fabrication of the VCO(Voltage controlled Oscillator) using RF circuit simulator GENESYS and electromagnetic field simulator EMpower Frequency range is fabricated VCO is 850 MHz ~ 950 MHz, which is used Colpitts Circuit. the fabricated VCO is consisted of resonator, oscillator and MSL(Microstrip Line) is used in LC tuning circuit.(operated by negative feedback) MSL(Microstrip Line), Varactor(Plastic package), low noise TR(SOT-23), chip inductor(1608), chip capacitor(1005), chip resistance(1005). 1005 type is used for sample fabrication of VCO. In the fabrication process, circuit pattern is screen printed on the alumina substrates of over 99.9% purity. Center frequency of the sample VCO is 850MHz at $V_T$=1.5V, while the simulated value was 1.0GHz at $V_T$=1.5V. Variable frequency range of the sample is 860~950MHz in contrast to the 1068~1100MHz of the simulated values.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.02a
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• pp.1-14
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• 2006

[ $\blacklozenge$ ] PCB에 있어서 Embedded passive 는chip을 직접 내장하는 방법과 특별한 특성을 갖는 재료 및 공법을 사용하여 chip 응 대치하는 방법이 있다. $\blacklozenge$ Embedded passive PCB가 적용될 수 있는 유력한 적용 분야는 소형화가가 요구되는 분야와 고속 특성이 요구되는 분야를 들 수 있고, 따라서, Module, SOP/SIP, Package substrate 등이 우선적으로 적용될 수 있는 분야다. $\blacklozenge$ Embedded capacitor를 적용한 경우, 일반적인 chip capacitor를 적용한 경우보다 더 좋은 전기적인 특성(SRF, Q)을 얻을 수 있으며, solder joint 등의 영향을 포함하면 더욱 좋은 특성이 얻어질 수 있다. $\blacklozenge$ Embedded passive 의 상용화를 위해서, 공차를 관리하는 방법의 개발과 공차에 대한 합리적인 규격을 설정하는 것이 우선 과제이다. $\blacklozenge$ Embedded resistor 의 경우, Laser trim을 적용하여 ${\pm}\;5\%$ 또는 그 이하의 공차를 실현할 수 있고, $30\;K\Omega/sq$. 의 고저항의 적용까지 가능하다. $\blacklozenge$ 고속 신호에서의 noise 감소, module, SIP/SOP 의 소형화를 실현하는데 Embedded passive(혹은 active)PCB 가 기여 할 수 있을 것이고, 이를 위하여 Set 업체, PCB 업체, 재료 업체간의 지속적인 협조가 필요할 것이다.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1141-1144
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• 2003

For proper communication with various types of IC-Card, multiple IC-Card interface complying with the IC-Card standard (ISO7816) is embedded and realized as a peripheral on the 32-bit RISC based system-on-a-chip. It provides the generation of either 3.3V or 5V power supply for the operation of the inserted IC-Card as well. IC-Card interface is divided into an analog front-end (AFE) and a digital back-end (DBE). The embedded DC-DC converters suitable for driving IC-Cards are incorporated in the AFE. The chip design for multiple IC-Card interface is implemented on a standard 0.35${\mu}{\textrm}{m}$ triple-metal double-poly CMOS process and is packaged in a 352-pin plastic ball grid array (PBGA). The total gate count is about 400,000, excluding the internal memory. Die area is 7890${\mu}{\textrm}{m}$ $\times$ 7890${\mu}{\textrm}{m}$.

• Journal of the Korean Society for Precision Engineering
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• v.7 no.4
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• pp.73-84
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• 1990

A burr has been defined as an undesirable projection of material formed as the result of plastic flow from a cutting or shearing operation. It is Unavoidable in all kinds of machining operation. This paper describe the burr formation mechanism which is based on the behavior of workpiece material during orthogonal machining of the clay on the milling machine. Specially in this report the rollover burr is dealt as a specific case of the chip formation in the final stage of cutting. The negative shear angle is introduced as an important features of burr formation. It is found that the burr formation process is divided into three stage-initiation, development of negative shearing, and formation of the burr with appropriate assumptions. Using above the burr formation mechanism, the size of burr can be estimated by cutting conditions.

• Transactions on Electrical and Electronic Materials
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• v.2 no.3
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• pp.28-32
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• 2001

It was studied in the present work how the thermal cycling performance of LOC (lead on chip) packages depends on the package construct or leadframe materials. First, package body thickness and Au wire diameter were manipulated for the selection of proper package design. Secondly, two different types of leadframe materials (i.e. copper and 52%Fe-48%Ni alloy) were tested to determine the better material for improved reliability margin of plastically encapsulated microelectronic packages. This work shows that manipulating package body thickness was more effective than an increase of Au wire from 23$\mu\textrm{m}$ to 33$\mu\textrm{m}$ for the prevention of wire debonding failure. Further, this work indicates that the LOC packages including the copper leadframes can be more susceptible to thermal cycling reliability degradation due to chip cracking than those including the alloy leadframes.

• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.3
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• pp.729-737
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• 1994

A three-dimensional finite element model of a 20-pin plastic dual-in-line package(PDIP) plugged into a PCE has been developed by using the finite element code ANSYS. The model has been used for thermal characterization of the package during its normal operation under natural convection cooling. Temperature distributions in the package and PCB are obtained from numerical analysis and compared with experimentally measured data. Various cases are assumed and analyzed to study the effects of package and PCB materials on thermal characteristics of PDIP with and without aluminum heatspreader. Thermal dissipation capability of PDIP is greatly increased due to copper die pad/lead frame and heatspreader. However, thermally induced stresses in the package and fatigue life of chip are improved for PDIP with Alloy 42 die pad/lead frame and no heatspreader. It is also found that the role of PCB on thermal characteristics of PDIP is very imporatant.

• Proceedings of the KSME Conference
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• 2001.11b
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• pp.400-404
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• 2001

A micro-PIV(particle image velocimetry) measurement has been conducted to investigate flow fields in such microfluidic devices as microchannels and micronozzle. The present study employs a state-of-art micro-PIV system which consists of epi-fluorescence microscope, 620nm diameter fluorescent seed particles and an 8-bit megapixel CCD camera. Velocity vector fields with a resolution of $6.7\times6.7{\mu}m$ has been obtained, and the attention has been paid on the effect of varying measurement conditions of particle diameter and particle concentration on the resulting PIV results. In this study, the microfluidic elements were fabricated on plastic chips by means of MEMS processes and a subsequent molding process. Flow fields in a variety of microchannels as well as micronozzle have been investigated.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1995.10a
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• pp.60-63
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• 1995

The behavior of the work materials in the chip-tool interface in extremely high strain rates and temperatures is more that of viscous liquids than that of normal solid metals. In these circumstances the principles of fluid mechanics can be invoked to describe the metal flow in the neighborhood of the cutting edge. In the present paper an Eulerian finite element model is presented that simulates metal flow in the vicinity of the cutting edge when machining a low carbon steel with carbide cutting tool. The work material is assumed to obey visco-plastic (Bingham solid) constitutive law and Von Mises criterion. Heat generation is included in the model, assuming adiabatic conditions within each element. the mechanical and thermal properties of the work material are accepted to vary with the temperature. The model is based on the virtual work-stream function formulation, emphasis is given on analyzing the formation of the stagnant metal zone ahead of the cutting edge. The model predicts flow field characteristics such as material velocity effective stress and strain-rate distributions as well as built-up layer configuration

• Transactions on Electrical and Electronic Materials
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• v.11 no.4
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• pp.178-181
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• 2010

An automotive IC voltage regulator which consists of one-chip based on a metal-oxide semiconductor field effect transistor (MOSFET) is investigated experimentally with three types of packaging. The closed type is filled with thermal silicone gel and covered with a plastic lid on the MOSFET. The half-closed type is covered with a plastic case but without thermal silicone gel on the MOSFET. Opened type is no lid without thermal silicone gel. In order to simulate the high temperature condition in engine bay, the operating circuit of the MOSFET is constructed and the surrounding temperature is maintained at $100^{\circ}C$. In the overshoot the maximum was mainly found at the half-closed packaging and the magnitude is dependent on the packaging type and the surrounding temperature. Also the impressed current decreased exponentially during the MOSFET operation.