• Title/Summary/Keyword: Plasma ploymerization

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Operating characteristics of Floating Gate Organic Memory (플로팅 게이트형 유기메모리 동작특성)

  • Lee, Boong-Joo
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.15 no.8
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    • pp.5213-5218
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    • 2014
  • Organic memory devices were made using the plasma polymerization method. The memory device consisted of ppMMA(plasma polymerization MMA) thin films as the tunneling and insulating layer, and a Au thin film as the memory layer, which was deposited by thermal evaporation. The organic memory operation theory was developed according to the charging and discharging characteristics of floating gate type memory, which would be measured by the hysteresis voltage and memory voltage with the gate voltage values. The I-V characteristics of the fabricated memory device showed a hysteresis voltage of 26 [V] at 60 ~ -60 [V] double sweep measuring conditions. The programming voltage was applied to the gate electrode in accordance with the result of this theory. A programming voltage of 60[V] equated to a memory voltage of 13[V], and 80[V] equated to a memory voltage of 18[V]. The memory voltage of approximately 40 [%]increased with increasing programming voltage. The charge memory layer charging or discharging according to the theory of the memory was verified experimentally.

Floating Gate Organic Memory Device with Tunneling Layer's Thickness (터널링 박막 두께 변화에 따른 부동 게이트 유기 메모리 소자)

  • Kim, H.S.;Lee, B.J.;Shin, P.K.
    • Journal of the Korean Vacuum Society
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    • v.21 no.6
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    • pp.354-361
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    • 2012
  • The organic memory device was made by the plasma polymerization method which was not the dry process but the wet process. The memory device consist of the styrene and MMA monomer as the insulating layer, MMA monomer as the tunneling layer and Au thin film as the memory layer which was fabricated by thermal evaporation method. The I-V characteristics of fabricated memory device got the hysteresis voltage of 27 V at 40/-40 V double sweep measuring conditions. At this time, the optimized structure was 7 nm of Au thin film as floating gate, 400 nm of styrene thin film as insulating layer and 30 nm of MMA thin film as tunneling layer. Therefore we got the charge trapping characteristics by the hysteresis voltage. From the paper, styrene indicated a good charge trapping characteristics better than MMA. In the future, we expect to make devices by using styrene thin film rather than Au thin film.