• Title/Summary/Keyword: Plasma dry etching

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Comparison of Dry Etching of AlGaAs/GaAs in High Density Inductively Coupled $BCl_3$ based Plasmas ($BCl_3$에 기초한 고밀도 유도결합 플라즈마에 의한 AlGaAs/GaAs 건식식각 비교)

  • ;;;;;S. J. Pearton
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2003.03a
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    • pp.63-63
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    • 2003
  • 플라즈마 공정은 DRAM, 이종접합 양극성 트랜지스터(HBTs), 레이저, 평면도파로(planar lightwave circuit)와 같은 전자소자 및 광조자 제작에 있어서 핵심 공정중의 하나이다. 최근 미세 구조의 크기가 극도로 감소하게 됨에 따라 실제 소작 제작에 있어서 미세한 모양을 식각하는 공정이 매우 중요하게 되었다. 그 중에서 고밀도 유도결합 플라즈마(high density inductively coupled plasma)를 이용한 기술은 빠르고 정확한 식각률, 우수한 식각 균일도와 높은 재현성 때문에 습식식각 기술보다 선호되고 있다. 본 연구는 평판형(planar) 고밀도 유도결합 플라즈마 식각장치를 이용하여 BCl$_3$와 BCl$_3$/Ar 플라즈마에 따른 AlGaAs/GaAs의 식각결과를 비교 분석하였다. 공정 변수는 ICP 소스(source power)파워, RIE 척(chuck) 파워, 공정 압력, 그리고 Ar 조성비(0-100%)이었다. BCl$_3$에 Ar을 첨가하게 되면 순수한 BCl$_3$ 플라즈마에서의 AlGaAs/GaAs 식각률(> 3000 $\AA$/min) 보다 분당 약 1000$\AA$ 이상 높은 식각률(>4000 $\AA$/min)을 나타내었다. 이 결과는 Ar 플라즈마의 이온보조(ion-assisted)가 식각률 증가에 기인한다고 예측된다. 그리고 전자주사 현미경(SEM)과 원자력간 현미경(AFM)을 사용하여 식각 후 표면 거칠기 및 수직 측벽도 둥을 분석하였다. 마지막으로 XPS를 이용하여 식각된 후에 표면에 남아 있는 잔류 성분 분석을 연구하였다. 본 결과를 종합하면 BCl$_3$에 기초한 평판형 유도결합 플라즈마는 AlGaAs/GaAs 구조의 식각시 많은 우수한 특성을 보여주었다.79$\ell/\textrm{cm}^3$, 0.016$\ell/\textrm{cm}^3$, 혼합재료 2는 0.045$\ell/\textrm{cm}^3$, 0.014$\ell/\textrm{cm}^3$, 혼합재료 3은 0.123$\ell/\textrm{cm}^3$, 0.017$\ell/\textrm{cm}^3$, 혼합재료 4는 0.055$\ell/\textrm{cm}^3$, 0.016$\ell/\textrm{cm}^3$, 혼합재료 5는 0.031$\ell/\textrm{cm}^3$, 0.015$\ell/\textrm{cm}^3$, 혼합재료 6은 0.111$\ell/\textrm{cm}^3$, 0.020$\ell/\textrm{cm}^3$로 나타났다. 3. 단일재료의 악취흡착성능 실험결과 암모니아는 코코넛, 소나무수피, 왕겨에서 흡착능력이 우수하게 나타났으며, 황화수소는 펄라이트, 왕겨, 소나무수피에서 다른 재료에 비하여 상대적으로 우수한 것으로 나타났으며, 혼합충진재는 암모니아의 경우 코코넛과 펄라이트의 비율이 70%:30%인 혼합재료 3번과 소나무수피와 펄라이트의 비율이 70%:30%인 혼합재료 6번에서 다른 혼합재료에 비하여 우수한 것으로 나타났으며, 황화수소의 경우 혼합재료에 따라 약간의 차이를 보였다. 4. 코코넛과 소나무수피의 경우 암모니아가스에 대한 흡착성능은 거의 비슷한 것으로 사료되며, 코코넛의 경우 전량을 수입에 의존하고 있다는 점에서 국내 조달이 용이하며, 구입 비용도 적게 소요되는 소나무수피를 사용하는 것이 경제적이라고 사료된다. 5. 마지막으로 악취제거 미생물균주를 접종한 소나무수피 70%와 펄라이트 30%의 혼합재료를 24시간동안 장기간 운전

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Copper Interconnection and Flip Chip Packaging Laboratory Activity for Microelectronics Manufacturing Engineers

  • Moon, Dae-Ho;Ha, Tae-Min;Kim, Boom-Soo;Han, Seung-Soo;Hong, Sang-Jeen
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.431-432
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    • 2012
  • In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

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The characteristic of InGaN/GaN MQW LED by different diameter in selective area growth method (선택성장영역 크기에 따른 InGaN/GaN 다중양자우물 청색 MOCVD-발광다이오드 소자의 특성)

  • Bae, Seon-Min;Jeon, Hun-Soo;Lee, Gang-Seok;Jung, Se-Gyo;Yoon, Wi-Il;Kim, Kyoung-Hwa;Yang, Min;Yi, Sam-Nyung;Ahn, Hyung-Soo;Kim, Suck-Whan;Yu, Young-Moon;Ha, Hong-Ju
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.22 no.1
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    • pp.5-10
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    • 2012
  • In general, the fabrications of the LEDs with mesa structure are performed grown by MOCVD method. In order to etch and separate each chips, the LEDs are passed the RIE and scribing processes. The RIE process using plasma dry etching occur some problems such as defects, dislocations and the formation of dangling bond in surface result in decline of device characteristic. The SAG method has attracted considerable interest for the growth of high quality GaN epi layer on the sapphire substrate. In this paper, the SAG method was introduced for simplification and fabrication of the high quality epi layer. And we report that the size of selective area do not affect the characteristics of original LED. The diameter of SAG circle patterns were choose as 2500, 1000, 350, and 200 ${\mu}m$. The SAG-LEDs were measured to obtain the device characteristics using by SEM, EL and I-V. The main emission peaks of 2500, 1000, 350, and 200 ${\mu}m$ were 485, 480, 450, and 445 nm respectively. The chips of 350, 200 ${\mu}m$ diameter were observed non-uniform surface and resistance was higher than original LED, however, the chips of 2500, 1000 ${\mu}m$ diameter had uniform surface and current-voltage characteristics were better than small sizes. Therefore, we suggest that the suitable diameter which do not affect the characteristic of original LED is more than 1000 ${\mu}m$.