• Title/Summary/Keyword: Pin 1 dimple

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Enhancement of Heat Transfer in Internal Passage using Pin-Fin with Jet Hole and Complex Pin-Fin-Dimple Array (제트홀이 설치된 핀-휜 및 핀-휜/딤플 복합 배열을 사용한 내부유로에서의 열전달 향상)

  • Park, Jun Su
    • Journal of Institute of Convergence Technology
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    • v.5 no.1
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    • pp.27-31
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    • 2015
  • A Pin-fin array is widely used to enhance the heat transfer in the internal cooling passage. The heat transfer distribution around the pin-fin is varied by the horseshoe vortex and flow separation. The difference of heat transfer coefficient induces the large thermal stress, which is one of the major reasons to break of hot components. So, it is required to enhance the heat transfer on the back side of pin-fin to solve the thermal stress problem. This study suggests the pin-fin with inclined jet hole and complex pin-fin/dimple array to enhance the heat transfer on the back side of pin-fin. The heat transfer coefficient is predicted by the numerical analysis, which is performed by CFX 14.0. The numerical results are obtained at Reynolds number, 10,000. The results show that the heat transfer on the back side of pin-fin is increased in both cases. Beside, the wake, which comes from dimple and jet, helps to develop the horseshoe vortex and increase the heat transfer on the next row pin-fin.

Tribological Characteristics in $40{\mu}m$ Dimple Pattern for Hexagonal Array (Hexagonal 배열 $40{\mu}m$ Dimple 패턴의 트라이볼로지적 특성)

  • Choi, Won-Sik;Chae, Young-Hoon;Umehara, Noritsugu
    • Tribology and Lubricants
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    • v.25 no.1
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    • pp.25-30
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    • 2009
  • 본 연구에서는 pin-on-disk 마찰 시험기를 통하여 Hexagonal 배열 $40{\mu}m$ Dimple 패턴의 효과를 실험하였다. 마찰 실험은 미끄럼 속도가 $0.06{\sim}0.34m/s$로 하였으며 마찰하중은 $20{\sim}100\;N$의 범위로 하였고, Dimple의 밀도는 $10{\sim}25%$의 범위로 제작하여 실험을 행하였다. 일반적으로 속도가 증가하고 하중이 감소할수록 마찰계수는 감소하는 경향을 나타내었으며, Dimple에 의한 마찰저감 효과는 속도가 $0.14{\sim}0.26m/s$의 범위에서 나타났다. $40{\mu}m$ Hexagonal 배열 Dimple 패턴의 마찰 특성에서는 밀도가 12.5%에서 가장 좋은 경향을 나타내었다.

IC Package Location and Pin1 Dimple Extraction Using Adaptive Multiple Thresholding (적응적 다중 이진화에 의한 IC 패키지 및 Pin1 딤플 검출)

  • 김민기
    • Proceedings of the Korean Information Science Society Conference
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    • 2001.10b
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    • pp.361-363
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    • 2001
  • 반도체 패키지의 마킹검사(marking inspection)를 위해서는 입력 영상으로부터 검사할 패키지의 정확만 위치 검출과 패키지 윗면에 나타난 제작사 로고, 문자, Pin1 딤플의 추출이 필수적이다. 본 연구는 마킹검사를 위한 선행 연구로 마킹검사를 수행할 때, 검사할 IC 패키지의 위치와 방향을 정확하게 검출하는 것을 목적으로 하고 있다. IC 패키지의 외곽을 구성하는 리드의 명도 값은 트레이의 명도 값과 큰 차이를 나타낸다. 그러나 IC 패키지의 방향을 나타내는 Pin1 딤플은 배경과 동일한 색상으로 다만 약간 오목하게 들어가서 명도 값의 차이가 미세하다. 이러한 두 가지 상이한 특징을 효과적으로 처리하기 위하여 적응적 다중 이진화 방법을 제시하였다. 76개의 명도 영상에 대한 실험 결과 제안된 이진화 방법은 매우 효과적이었으며, 이진화된 영상으로부터 IC 패키지의 정확한 위치 검출과 방향 확인이 가능하였다.

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Non-HF Type Etching Solution for Slimming of Flat Panel Display Glass (평판디스플레이용 유리의 박판화공정을 위한 비불산형 식각액)

  • Lee, Chul-Tae
    • Applied Chemistry for Engineering
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    • v.27 no.1
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    • pp.101-109
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    • 2016
  • The purpose of this research was to develop a flat panel display device's glass etchant which can replace hydrofluoric acid. The glass etchant was composed of 18~19% wt% of ammonium hydrogen fluoride, 24~25 wt% of sulfuric acid, 45~46 wt% of water, 4~5 wt% of sulfate and 7~8 wt% of fluoro-silicate. By replenishing the etchant which has the amount of 5% of initial solution's mass, it was possible to reuse the etchant continuously. The developed etchant showed $5{\mu}m/min$ of etching rate at $30^{\circ}C$. The reusable etchant, with replenishing 5% of initial etchant mass showed the stable etching rate, which has the deviation of less than $0.1{\mu}m/min$ etching rate. The glass surface of flat panel display device created from our etching process was in good condition with any defects such as pin hole and dimple.

An Adaptive Multi-Level Thresholding and Dynamic Matching Unit Selection for IC Package Marking Inspection (IC 패키지 마킹검사를 위한 적응적 다단계 이진화와 정합단위의 동적 선택)

  • Kim, Min-Ki
    • The KIPS Transactions:PartB
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    • v.9B no.2
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    • pp.245-254
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    • 2002
  • IC package marking inspection system using machine vision locates and identifies the target elements from input image, and decides the quality of marking by comparing the extracted target elements with the standard patterns. This paper proposes an adaptive multi-level thresholding (AMLT) method which is suitable for a series of operations such as locating the target IC package, extracting the characters, and detecting the Pinl dimple. It also proposes a dynamic matching unit selection (DMUS) method which is robust to noises as well as effective to catch out the local marking errors. The main idea of the AMLT method is to restrict the inputs of Otsu's thresholding algorithm within a specified area and a partial range of gray values. Doing so, it can adapt to the specific domain. The DMUS method dynamically selects the matching unit according to the result of character extraction and layout analysis. Therefore, in spite of the various erroneous situation occurred in the process of character extraction and layout analysis, it can select minimal matching unit in any environment. In an experiment with 280 IC package images of eight types, the correct extracting rate of IC package and Pinl dimple was 100% and the correct decision rate of marking quality was 98.8%. This result shows that the proposed methods are effective to IC package marking inspection.