• Journal of Advanced Navigation Technology
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• v.22 no.5
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• pp.429-435
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• 2018

In radar systems, FFT (fast Fourier transform) operation is necessary to obtain the range and velocity of target, and the design of an FFT processor which operates at high speed is required for real-time implementation. The perfect shuffle network is suitable for high-speed FFT processor. In particular, twice perfect shuffle network based on radix-4 is preferred for very high-speed FFT processor. Moreover, radar systems that requires various velocity resolution should support scalable FFT points. In this paper, we propose a 8~1024-point scalable FFT processor based on twice perfect shuffle network algorithm and present hardware design and implementation results. The proposed FFT processor was designed using hardware description language (HDL) and synthesized to gate-level circuits using $0.65{\mu}m$ CMOS process. It is confirmed that the proposed processor includes logic gates of 3,293K.

• Journal of the Optical Society of Korea
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• v.1 no.1
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• pp.52-59
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• 1997

In this paper, we propose a system design for a parallel3-dimensional optical interconnection network utilizing variable grating mode liquid crystal devices (VGM LCD's) which are optical transducers capable of performing intensity-to-spatial-frequency conversion. The proposed system performs real-time, reconfigurable, but blocking and nonbroadcasting 3-dimensional optical interconnections. The operating principles of the 3-D optical interconnection network are described, and some of the fundamental limitations are addressed. The system presented in this paper can be directly used as a configuration of switching elements for the 2-D optical perfect-shuffle dynamic interconnection network, as well as for a B-ISDN photonic switching system.