• Transactions on Semiconductor Engineering
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• v.2 no.4
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• pp.13-20
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• 2024

This work presents a Cross-Coupled Differential Rectifier (CCDR) with an improved gate bias voltage topology, utilizing the rectifier's stage output-referred bias to increase the gate bias. The primary objective is to develop a 5.8 GHz rectifier operating at a much lower input power. The target input power is -10 dBm, which is insufficient to meet the threshold voltage of typical transistors (usually around 300 to 450 mV). Although the input power is inadequate to turn on the transistor fully, the transistor still generates a conduction swing as it operates in the sub-threshold region. Since the ratio of transconductance to current is very high in this region, an additional voltage bias is crucial to increase the swing and generate a higher output voltage. To achieve this, the proposed rectifier implements an output-connected bias for the main rectifying transistors, generating additional bias to enhance the conduction swing. Furthermore, the gate terminal is connected in parallel to the rectifier's lowest node, allowing the input voltage to be controlled by specific transistors on the proposed gate bias nodes. The design is simulated with an ideal antenna (with a 50 Ω antenna resistance) under various load and matching network conditions to match the rectifier's input impedance and maximize performance. The proposed technique, implemented using 28 nm technology, achieves a peak conversion efficiency (PCE) of 65.14%, with a total dynamic range of 21 dBm across various loads. The design generates an output of 0.8 V with a 10㏀ and 100pF load and can be extended within the dynamic range up to 1.5 V.

• 한국신재생에너지학회:학술대회논문집
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• 2011.11a
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• pp.57.1-57.1
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• 2011

We studied the performance of CdSe nanoparticle in the active layer of organic photovoltaics (OPVs) by changing concentration of the CdSe NPs in the P3HT:PCBM layer. We observed that the absorption peak value gradually increases with the increasing amount of CdSe NPs at 600nm wave length. However, the electrical properties of OPVs correspond less with the tendency of UV/visible result. The highest performance was shown with 10% of CdSe NPs. The device performance decreased after 10% of CdSe NPs, this shows the dependencies of performanc of hybrid solar cells on the CdSe NPs loading amount. The resulting OPVs with 10 % of CdSe NPs show a short circuit current density ($J_{sc}$) of $6.96mA/cm^2$, open circuit voltage ($V_{oc}$) of 0.61V, fill factor (FF) of 0.59, and power conversion efficiency (PCE) of 2.53% under AM 1.5 ($100mW/cm^2$).

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.85-90
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• 2017

The $TiCl_4$ as a blocking material is adsorbed in the mesoporous $TiO_2$ electron transfer layer(ETL) of the Perovskite solar cell to prevent the direct contact between the FTO electrode and the photoactive layer(AL), and facilitate the movement of the electrons between $TiO_2:TiCl_4$ ETL and Perovskite AL to improve the photoelectric conversion efficiency(PCE). The structure of the perovskite solar cell is FTO/$TiO_2:TiCl_4$/Perovskite($CH_3NH_3PbI_3$)/spiro-OMeTAD/Ag. It was investigated that the dipping time of the $TiO_2$ into $TiCl_4$ aqueous solution affects on the photoelectric characteristics of the device. By the dipping for 30 minutes, the PCE of the perovskite solar cell with the $TiO_2:TiCl_4$ ETL was the highest 10.46%, which is 27% higher than the cell with $TiO_2$ ETL. From SEM, EDS, and XRD characterization on the $TiO_2:TiCl_4$ ETL and the perovskite AL, it was measured that the decrease of the porosity of the $TiO_2$ layer, the detection of the Cl component by the $TiCl_4$ adsorption, the cube-type morphology of perovskite AL, and shift of the $PbI_2$ peak of the perovskite AL. From these results, it was confirmed that the $TiO_2:TiCl_4$ ETL and the perovskite AL were formed.