• Title/Summary/Keyword: Pattern matching hardware

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A Hardware-Based String Matching Using State Transition Compression for Deep Packet Inspection

  • Kim, HyunJin;Lee, Seung-Woo
    • ETRI Journal
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    • v.35 no.1
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    • pp.154-157
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    • 2013
  • This letter proposes a memory-based parallel string matching engine using the compressed state transitions. In the finite-state machines of each string matcher, the pointers for representing the existence of state transitions are compressed. In addition, the bit fields for storing state transitions can be shared. Therefore, the total memory requirement can be minimized by reducing the memory size for storing state transitions.

Development of an Integer Algorithm for Computation of the Matching Probability in the Hidden Markov Model (I) (은닉마르코브 모델의 부합확률연산의 정수화 알고리즘 개발 (I))

  • 김진헌;김민기;박귀태
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.31B no.8
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    • pp.11-19
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    • 1994
  • The matching probability P(ο/$\lambda$), of the signal sequence(ο) observed for a finite time interval with a HMM (Hidden Markov Model $\lambda$) indicates the probability that signal comes from the given model. By utilizing the fact that the probability represents matching score of the observed signal with the model we can recognize an unknown signal pattern by comparing the magnitudes of the matching probabilities with respect to the known models. Because the algorithm however uses floating point variables during the computing process hardware implementation of the algorithm requires floating point units. This paper proposes an integer algorithm which uses positive integer numbers rather than float point ones to compute the matching probability so that we can economically realize the algorithm into hardware. The algorithm makes the model parameters integer numbers by multiplying positive constants and prevents from divergence of data through the normalization of variables at each step. The final equation of matching probability is composed of constant terms and a variable term which contains logarithm operations. A scheme to make the log conversion table smaller is also presented. To analyze the qualitive characteristics of the proposed algorithm we attatch simulation result performed on two groups of 10 hypothetic models respectively and inspect the statistical properties with repect to the model order the magnitude of scaling constants and the effect of the observation length.

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A High-speed Packet Filtering System Architecture in Signature-based Network Intrusion Prevention (시그내쳐 기반의 네트워크 침입 방지에서 고속의 패킷 필터링을 위한 시스템 구조)

  • Kim, Dae-Young;Kim, Sun-Il;Lee, Jun-Yong
    • Journal of KIISE:Computer Systems and Theory
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    • v.34 no.2
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    • pp.73-83
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    • 2007
  • In network intrusion prevention, attack packets are detected and filtered out based on their attack signatures. Pattern matching is extensively used to find attack signatures and the most time-consuming execution part of Network Intrusion Prevention Systems(NIPS). Pattern matching is usually accelerated by hardware and should be performed at wire speed in NIPS. However, that alone is not good enough. First, pattern matching hardware should be able to generate sufficient pattern match information including the pattern index number and the location of the match found at wire speed. Second, it should support pattern grouping to reduce unnecessary pattern matches. Third, it should always have a constant worst-case performance even if the number of patterns is increased. Finally it should be able to update patterns in a few minutes or seconds without stopping its operations, We propose a system architecture to meet the above requirement. The system architecture can process multiple pattern characters in parallel and employs a pipeline architecture to achieve high speed. Using Xilinx FPGA simulation, we show that the new system stales well to achieve a high speed oner 10Gbps and satisfies all of the above requirements.

A Rule-Based System for VLSI Gate-Level Logic Optimization (VLSI 게이트 레벨 논리설계 최적화를 위한 Rule-Based 시스템)

  • Lee, Seong-Bong;Chong, Jong-Wha
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.1
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    • pp.98-103
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    • 1989
  • A new system for logic optimization at gate-level is proposed in this paper. Ths system is rule-based, i which the rules represent the local trnsformation replacing a portion of circuits with the simplified equivalent circuits. In this system, 'rule generalization' and 'local optimization' are proposed for effective pattern matching. Rule generalization is used to reduce the circuit-search for pattern matching, and local optimization, to exclude unnecessary circuit-search. In additionk, in order to reduce unnecessary trial of pattern matching, the matching order of circuit patern is included in the rule descriptions. The effectiveness of this system is shown by its application ot the circuits which are generated by a hardware compiler.

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Regular Expression Matching Processor Architecture Supporting Character Class Matching (문자클래스 매칭을 지원하는 정규표현식 매칭 프로세서 구조)

  • Yun, SangKyun
    • Journal of KIISE
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    • v.42 no.10
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    • pp.1280-1285
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    • 2015
  • Many hardware-based regular expression matching architectures are proposed for high performance matching. In particular, regular expression processors such as ReCPU and SMPU perform pattern matching in a similar approach to that used in general purpose processors, which provide the flexibility when updating patterns. However, these processors are inefficient in performing class matching since they do not provide character class matching capabilities. This paper proposes an instruction set and architecture of a regular expression matching processor, which can support character class matching. The proposed processor can efficiently perform character class matching since it includes character class, character range, and negated character class matching capabilities.

Design and Implementation of a Host Interface for a Regular Expression Processor (정규표현식 프로세서를 위한 호스트 인터페이스 설계 및 구현)

  • Kim, JongHyun;Yun, SangKyun
    • KIISE Transactions on Computing Practices
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    • v.23 no.2
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    • pp.97-103
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    • 2017
  • Many hardware-based regular expression matching architectures have been proposed for high-performance matching. In particular, regular expression processors, which perform pattern matching by treating the regular expressions as the instruction sequence like general purpose processors, have been proposed. After instruction sequence and data are provided in the instruction memory and data memory, respectively, a regular expression processor can perform pattern matching. To use a regular expression processor as a coprocessor, we need the host interface to transfer the instruction and data into the memory of a regular expression processor. In this paper, we design and implement the host interface between a host and a regular expression processor in the DE1-SoC board and the application program interface. We verify the operations of the host interface and a regular expression processor by executing the application programs which perform pattern matching using the application program interface.

A Pattern-based Query Strategy in Wireless Sensor Network

  • Ding, Yanhong;Qiu, Tie;Jiang, He;Sun, Weifeng
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.6 no.6
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    • pp.1546-1564
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    • 2012
  • Pattern-based query processing has not attracted much attention in wireless sensor network though its counterpart has been studied extensively in data stream. The methods used for data stream usually consume large memory and much energy. This conflicts with the fact that wireless sensor networks are heavily constrained by their hardware resources. In this paper, we use piece wise representation to represent sensor nodes' collected data to save sensor nodes' memory and to reduce the energy consumption for query. After getting data stream's and patterns' approximated line segments, we record each line's slope. We do similar matching on slope sequences. We compute the dynamic time warping distance between slope sequences. If the distance is less than user defined threshold, we say that the subsequence is similar to the pattern. We do experiments on STM32W108 processor to evaluate our strategy's performance compared with naive method. The results show that our strategy's matching precision is less than that of naive method, but our method's energy consumption is much better than that of naive approach. The strategy proposed in this paper can be used in wireless sensor network to process pattern-based queries.

A Study on Voice Recognition Pattern matching level for Vehicle ECU control (자동차 ECU제어를 위한 음성인식 패턴매칭레벨에 관한 연구)

  • Ahn, Jong-Young;Kim, Young-Sub;Kim, Su-Hoon;Hur, Kang-In
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.10 no.1
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    • pp.75-80
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    • 2010
  • Noise handing is very important in voice recognition of vehicle environment. that has been studying about to hardware and software approach. hardware method that is noise filter circuit design, basically using Low-pass filter. it was shown a good result. and the side of software that has been developing about to algorithm for Noise canceler, NN(neural network), etc. in this paper we have analysis about to classified parameter pattern matting level for voice recognition on car noise environment that use of DTW(Dynamic Time Warping) which is applicable time series pattern recognition algorithm.

Development of a Door System by Speaker Verification Using Weighted Cepstrum and Single Average Pattern

  • Kyung, Youn-Jeong
    • The Journal of the Acoustical Society of Korea
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    • v.15 no.2E
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    • pp.60-68
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    • 1996
  • In this paper, we implement the door lock system based on pattern matching technique for speaker recognition using DTW. In this study, major features of our system are summarized as follows:(1) Make the average reference pattern using DTW. This method keeps the high recognition rate compared with the other systems whose performances degrade rapidly as time goes on. (2) Use F-ratio values of the cepstral coefficients. We find that the weighted cepstral reveals an effect on intensifying the difference between th customer and the imposter. The system hardware is composed of two parts : the door lock part and the speaker recognition processing part. We use an 8051 microprocessor in the door lock park for serial communication with host processor to open or close the lock. Using our system, we obtain speaker recognition rate of about 99.5%.

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Development of an edge-based point correlation algorithm for fast and stable visual inspection system (고속 검사자동화를 위한 에지기반 점 상관 알고리즘의 개발)

  • 강동중;노태정
    • Journal of Institute of Control, Robotics and Systems
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    • v.9 no.8
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    • pp.640-646
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    • 2003
  • We presents an edge-based point correlation algorithm for fast and stable visual inspection system. Conventional algorithms based on NGC(normalized gray-level correlation) have to overcome some difficulties in applying automated inspection systems to real factory environment. First of all, NGC algorithms involve highly complex computation and thus require high performance hardware for realtime process. In addition, lighting condition in realistic factory environments is not stable and therefore intensity variation from uncontrolled lights gives many troubles for applying NGC directly as pattern matching algorithm. We propose an algorithm to solve these problems, using thinned and binarized edge data, which are obtained from the original image. A point correlation algorithm with the thinned edges is introduced with image pyramid technique to reduce the computational complexity. Matching edges instead of using original gray-level image pixels overcomes problems in NGC method and pyramid of edges also provides fast and stable processing. All proposed methods are proved by the experiments using real images.