• Proceedings of the KIPE Conference
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• 전력전자학회 2018년도 전력전자학술대회
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• pp.352-353
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• 2018

본 논문은 250kW급 에너지저장장치(ESS)를 이용한 배전계통 일체형 전력변환 장치의 병렬운전 및 부분운전 방식을 제안한다. 제안하는 ESS의 기능은 배전선로에 4식 PCS로 1MW급 계통 연계형 병렬운전, 4식의 ESS 중 1식 이상의 고장에 대해서 모든 ESS가 정지하는 것이 아닌 고장 시료만 정지하는 부분 운전 방식의 운영 사례에 대한 고찰이다. 나아가 병렬운전과 부분운전으로 수용가 부문에서 상업 가정 전력 최적소비 방안을 도출한다. 제안하는 구조는 DC Link를 공유하지 않는 일체형 모형으로 내부 순환전류 회피 가능하다. 본 구조는 시뮬레이션, Prototype, 현장 시험으로 기 성능을 검증하였다.

• Proceedings of the KIEE Conference
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• 대한전기학회 1995년도 하계학술대회 논문집 B
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• pp.823-825
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• 1995

This paper presents an efficient and robust robot path planning technique that can always find a path, if one exists, in a densely cluttered, unknown and unstructured obstacle environment. The terrain in which the robot is expected to navigate is represented as a tesselated grid of square cells. The generated path is resolution complete and also resolution optimal once the terrain is fully explored by the robot or all the information about the terrain is given. The technique enables the accurate wave propagation to the diagonally adjacent cells and facilitates the implementations of various essential features for a real-time path planner such as partial updates and parallel computations.

• Journal of the Korean Institute of Telematics and Electronics C
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• 제35C권3호
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• pp.46-58
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• 1998

Multi-disk data allocation problem examined in this paper is to find a method to distribute a Binary Cartesian Product File on multiple disks to maximize parallel disk I/O accesses for partial match retrieval. This problem is known to be NP-hard, and heuristkc approaches have been applied to obtain sub-optimal solutions. Recently, efficient methods have been proposed with a restriction that the number of disks in which files are stored should be power of 2. In this paper, we propose a new disk Allocation method based on Genetic Algorithm(GA) to remove the restriction on the number of disks to be applied. Using the schema theory, we prove that our method can find a near-optimal solutionwith high probability. We compare the quality of solution derived by our method with General Disk Modulo, Binary Disk Modulo, and Error Correcting Code methods through the simulation. The simulation results show that proposed GA is superior to GDM method in all cases and provides comparable performance to the BDM method which has a restriction on the number of disks.

• Journal of the Korean Institute of Telematics and Electronics C
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• 제34C권6호
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• pp.22-27
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• 1997

This paper propose a novel VLSI architecture for a multiplierless FIR filter chip providing variable-length taps. To change the number of taps, we propose two special features called a data-reuse structure and a recurrent-coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and a modulo unit. Since multipliers occupy large VLSI area, a multiplierless filter chip meeting real-time requirement can save large area. We propose a modified bit-serial multiplication algorithm to compute two partial products in parallel, and thus, the proposed filter is twice faster and has smaller hardware than previous multiplierless filters. We developed VHDL models and performed logic synthesis using the 0.8.mu.m SOG (sea-of-gate) cell library. The chip has only 9,507 gates, was fabricated, and is running at 77MHz.

• Structural Engineering and Mechanics
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• 제34권5호
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• pp.549-561
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• 2010

In this paper, free vibration analyses of a parallel placed twin pipe system simulated by simply supported-simply supported and fixed-fixed Euler-Bernoulli beams resting on Winkler elastic soil are presented. The motion of the system is described by a homogenous set of two partial differential equations, which is solved by a simulation method called the Differential Transform Method (DTM). Free vibrations of an elastically connected twin pipe system are realized by synchronous and asynchronous deflections. The results of the presented theoretical analyses for simply supported Euler-Bernoulli beams are compared with existing ones in open literature and very good agreement is demonstrated.

• Bulletin of the Korean Chemical Society
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• 제17권5호
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• pp.447-452
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• 1996

Three conformational isomers of calix[4]arene butanoate were isolated from the reaction of calix[4]arene and butanoyl chloride in the presence of NaH and their structures were determined by NMR spectra as 1,2-alternate 2a, partial cone 2b and 1,3-alternate conformer 2c, respectively. The crystal structure of 2a has been determined by X-ray diffraction method. The crystals are monoclinic, space group C2/c, a=18.435 (4), b=13.774 (2), c=16.941 (3) Å, β=116.23 (1)°, Z=4, V=3858.8 (12)Å3, Dc=1.21 g cm-3, Dm=1.21 g cm-3. The molecule is in the 1,2-alternate conformation. It has two-fold symmetry axis along the line connecting between C (7AA') and C (7BB') parallel to the b axis of crystal lattice.

• Current Optics and Photonics
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• 제3권4호
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• pp.336-341
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• 2019

This paper proposes an optical system where the organic compound content in water is determined by using an ultraviolet (UV) LED (280 nm) and photodetector. The results obtained by the proposed prototype LED spectroscopy system, which includes a single photodetector and two parallel sample holders, are calculated by applying partial least square regression; the values are highly correlated with the actual concentrations of potassium hydrogen phthalate solutions, with an adjusted coefficient of determination about 0.996. Moreover, the total organic carbon values derived from the UV-Vis spectrometer of real samples (lake, river and sea water) differed little from those obtained by the LED spectroscopy. We confirm that the fast, sensitive, and compact LED sensor system can be readily configured for real-time monitoring of organic compounds in water.

• Journal of applied mathematics & informatics
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• 제41권2호
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• pp.401-411
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• 2023

The effects of longitudinal velocity dusty fluid flow in a weak magnetic field are investigated in this paper. An external uniform magnetic field parallel to the flow of dusty fluid influences the flow of dusty fluid. Besides that, the problem under investigation is completely defined in terms of identifying parameters such as longitudinal velocity (u), Hartmann number (M), dust particle interactions β, stock resistance γ, Reynolds number (Re) and magnetic Reynolds number (Rm). While using suitable transformations of resemblance, The governing partial differential equations are transformed into a system of ordinary differential equations. The Hankel Transformation is used to solve these equations numerically. The effects of representing parameters on the fluid phase and particle phase velocity flow are investigated in this analysis. The magnitude of the fluid particle is reduced significantly. The result indicates the magnitude of the particle reduced significantly. Although some of our numerical solutions agree with some of the available results in the literature review, other results differs because of the effect of the introduced magnetic field.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제49권7호
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• pp.39-49
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• 2012

Demand for high resolution video services leads to active studies on high speed video processing. Especially, widespread deployment of multi-core systems accelerates researches on high resolution video processing based on parallelization of multimedia software. Previously proposed parallelization approach could improve the decoding performance. However, some parallelization methods did not consider the entropy decoding and others considered only a partial decoding parallelization. Therefore, we consider parallel entropy decoding integrated with other parallel video decoding process on a multi-core system. We propose a novel parallel decoding method called Integrated Parallelization. We propose a method on how to optimize the parallelization of video decoding when we have a multi-core system with many cores. We parallelized the KTA 2.7 decoder with the proposed technique on an Intel i7 Quad-Core platform with Intel Hyper-Threading technology and multi-threads scheduling. We achieved up to 70% performance improvement using IP method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제40권6호
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.