• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.27-35
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• 1997

In this paper, we propose a new scheme for the generation of partial products for VLSI fast parallel multiplier. It adopts a new encoding method which halves the number of partial products using 2x2 submultipliers and rearrangement of primitive partial products. The true 4-input CSA can be achieved with appropriate rearrangement of primitive partial products out of 2x2 submultipliers using the newly proposed theorem on binary number system. A 16bit x 16bit multiplier has been desinged using the proposed method and simulated to prove that the method has comparable speed and area compared to booth's encoding method. Much smaller and faster multiplier could be obtained with far optimization. The proposed scheme can be easily extended to multipliers with inputs of higher resolutions.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2287-2290
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• 2003

In this paper, an image vector quantization method is proposed not only to improve the compression ratio but also to reduce the computation cost. The proposed method could save the computation cost of codebook generation and encoding by using the modified LBG algorithm of Partial Search Partial Distortion (PSPD) in wavelet domain, by which the code book was constructed together with the partial codebook search, the partial code vector elements, and the interruption criterion. We have designed and implemented the vector quantizer to verify the improvement in reducing compression ratio in encoding processing and reducing the computation cost.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12C
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• pp.1231-1238
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• 2005

This paper presents a new fast encoding algorithm for image vector quantization that incorporates the partial distances of multiple features with a multidimensional look-up table (LUT). Although the methods which were proposed earlier use the multiple features, they handles the multiple features step by step in terms of searching order and calculating process. On the other hand, the proposed algorithm utilizes these features simultaneously with the LUT. This paper completely describes how to build the LUT with considering the boundary effect for feasible memory cost and how to terminate the current search by utilizing partial distances of the LUT Simulation results confirm the effectiveness of the proposed algorithm. When the codebook size is 256, the computational complexity of the proposed algorithm can be reduced by up to the $70\%$ of the operations required by the recently proposed alternatives such as the ordered Hadamard transform partial distance search (OHTPDS), the modified $L_2-norm$ pyramid ($M-L_2NP$), etc. With feasible preprocessing time and memory cost, the proposed algorithm reduces the computational complexity to below the $2.2\%$ of those required for the exhaustive full search (EFS) algorithm while preserving the same encoding quality as that of the EFS algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11C
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• pp.901-906
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• 2010

Low density parity check (LDPC) code, first introduced by Gallager and re-discovered by MacKay et al, has attracted researcher's interest mainly due to their performance and low decoding complexity. It was remarkable that the performance is very close to Shannon capacity limit under the assumption of having long codeword length and iterative decoder. However, comparing to turbo codes widely used in the current mobile communication, the encoding complexity of LDPC codes has been regarded as the drawback. This paper proposes a solution for DVB-S2 LDPC encoder to reduce the encoder latency. We use the fast IRA encoder that use the transformation of the parity check matrix into block-wise form and the partial parallel process to reduce the number of system clocks for the IRA code encoding. We compare the proposed encoder with the current DVB-S2 encoder to show that the performance of proposal is better than that of the current DVB-S2 encoder.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.50-58
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• 2013

In this paper, parallel decimal fixed-point multiplier which uses the limited range of Singed-Digit number encoding and the reduction step is proposed. The partial products are generated without carry propagation delay by encoding a multiplicand and a multiplier to the limited range of SD number. With the limited range of SD number, the proposed multiplier can improve the partial product reduction step by increasing the number of possible operands for multi-operand SD addition. In order to estimate the proposed parallel decimal multiplier, synthesis is implemented using Design Compiler with SMIC 180nm CMOS technology library. Synthesis results show that the delay of proposed parallel decimal multiplier is reduced by 4.3% and the area by 5.3%, compared to the existing SD parallel decimal multiplier. Despite of the slightly increased delay and area of partial product generation step, the total delay and area are reduced since the partial product reduction step takes the most proportion.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.23-30
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• 1998

We present a partial bus-invert coding scheme for system-level power optimization. In the proposed scheme, we select a sub-group of bus lines involved in bus encoding to avoid unnecessary inversion of bus lines not in the sub-group thereby reducing the total number of bus transitions. We propose a heuristic algorithm that selects the sub-group of bus lines for bus encoding. Experiments on benchmark examples indicate that the partial bus-invert coding reduces the total bus transitions by 62.6% on the average, compared to that of the unencoded patterns. We also compare the performance of the proposed heuristic algorithm with that of simulated annealing, which shows that it is highly efficient.

• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.2
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• pp.409-416
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• 2024

With the expansion of floating-point operation requirements for fast high-speed data signal processing and logic operations, the speed of the floating-point operation unit is the key to affect system operation. This paper studies the performance characteristics of different floating-point multiplier schemes, completes partial product compression in the form of carry and sum, and then uses a carry look-ahead adder to obtain the result. Intel Quartus II CAD tool is used for describing Verilog HDL and evaluating performance results of the floating point multipliers. Floating point multipliers are analyzed and compared based on area, speed, and power consumption. The FMAX of modified Booth encoding with Wallace tree is 33.96 Mhz, which is 2.04 times faster than the booth encoding, 1.62 times faster than the modified booth encoding, 1.04 times faster than the booth encoding with wallace tree. Furthermore, compared to modified booth encoding, the area of modified booth encoding with wallace tree is reduced by 24.88%, and power consumption of that is reduced by 2.5%.

• Horticulture, Environment, and Biotechnology : HEB
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• v.59 no.6
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• pp.857-864
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• 2018

Previous studies have not detected transcripts of the gene encoding anthocyanidin synthase (ANS) in white pomegranates (Punica granatum L.) and suggest that a large-sized insertion in the coding region of the ANS gene might be the causal mutation. To elucidate the identity of the putative insertion, 3887-bp 5' and 3392-bp 3' partial sequences of the insertion site were obtained by genome walking and a gene coding for an expansin-like protein was identified in these genome-walked sequences. An identical protein (GenBank accession OWM71963) isolated from pomegranate was identified from BLAST search. Based on information of OWM71963, a 5.8-Mb scaffold sequence with genes coding for the expansin-like protein and ANS were identified. The scaffold sequence assembled from a red pomegranate cultivar also contained all genome-walked sequences. Analysis of positions and orientations of these genes and genome-walked sequences revealed that the 27,786-bp region, including the 88-bp 5' partial sequences of the ANS gene, might be translocated into an approximately 22-kb upstream region in an inverted orientation. Borders of the translocated region were confirmed by PCR amplification and sequencing. Based on the translocation mutation, a simple PCR codominant marker was developed for efficient genotyping of the ANS gene. This molecular marker could serve as a useful tool for selecting desirable plants at young seedling stages in pomegranate breeding programs.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.4
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• pp.278-285
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• 2011

This paper makes an analysis of the encoding structure and the decoding algorithm proposed by the DVB-S2 specification. The methods of implementing the LDPC decoder are fully serial decoder, the partially parallel decoder and the fully parallel decoder. The partial parallel scheme is the efficient selection to achieve appropriate trade-offs between hardware complexity and decoding speed. Therefore, this paper proposed an efficient memory structure for check node update block, bit node update block, and LLR memory.

• BMB Reports
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• v.29 no.2
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• pp.137-141
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• 1996

A partial cDNA encoding a Korean radish isoperoxidase was obtained from a cDNA library prepared from 9 day old radish root. In order to obtain Korean radish isoperoxidase cDNA, 5' RACE (rapid amplification cDNA end) PCR was performed and a cDNA (prxK1) encoding a complete structural protein was obtained by RT (reverse transcription)-PCR. Sequence analysis revealed that the length of the cDNA was 945 base pairs, and that of the mRNA transcript was ca. 1.6 kb. The deduced amino acid of the protein were composed of 315 amino acid residues and the protein was 92% homologous to turnip peroxidase, and 46% to 50% homologous to other known peroxidases. The 945 bp cDNA encoding Korean radish isoperoxidase was overexpressed in Escherichia coli up to approximately 9% of total cellular protein. The recombinant fusion protein exhibited 43 kDa on SDS-PAGE analysis and the activity level of the recombinant nonglycosylated protein was two fold higher in IPTG induced cell extracts than that of uninduced ones.