• Current Optics and Photonics
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• v.2 no.5
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• pp.400-406
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• 2018

The Semiconductor Optical Amplifier (SOA)-based Mach-Zehnder interferometer is a major contributor in all-optical digital processing and optical computation. Optical tree architecture provides one of the new, alternative schemes for integrated all-optical arithmetic and logical operations. In this paper, we propose an all-optical 3-bit integrated parity generator and checker using SOA-MZI-based optical tree architecture. The proposed scheme, able to process input signals at a desired operating wavelength, has been characterized using RZ-modulated signals at 10 Gbps. The maximum extinction ratios achieved at the output of the parity generator and checker are 10 dB and 8 dB respectively.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.50-55
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• 2001

In this paper, a 8bit parity checker/generator is designed using a new gate which is proposed to implement the exclusive or(XOR) and exclusive-nor(XNOR) functions for low power consumption on transistor level. Conventional XOR/XNOR gate such as CPL, DPL and CCPL designed to reduce the power consumption has an inverter to get the full swing output signals. But this inverter consumes the major part of power and causes the time delay on CMOS circuits. Thus a new technique was adopted not utilizing inverter in the circuits. The results of simulation by Hspice shows 33% of power reduction compared with CCPL gate when A 8 bit parity checker was made with the proposed new gate using $0.8{\mu}mCMOS$ technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1149-1159
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• 1998

This paper presents the Controllable Self-Checking(CSC) Checker at which can be used the Fault-Tolerant System with the redundancy. According to the critical level of output(of system), especially, it can be instructed the time if it has to check the output or not. We adop the deterministic test, performed on-line, to detect the faults with a minimal test set. The results show the Parity 2-rail checker(P-TRC) which is designed much simpler than the checker has the higher fault coverage than the existent checker.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.156-163
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• 2012

Recently, Information Hiding Technology are becoming increasingly demanding in the field of international security, military and medical image This paper proposes data hiding technique utilizing parity checker for gray level image. many researches have been adopted LSB substitution and XOR operation in the field of steganography for the low complexity, high embedding capacity and high image quality. But, LSB substitution methods are not secure through it's naive mechanism even though it achieves high embedding capacity. Proposed method replaces LSB of each pixel with XOR(between the parity check bit of other 7 MSBs and 1 Secret bit) within one pixel. As a result, stego-image(that is, steganogram) doesn't result in high image degradation. Eavesdropper couldn't easily detect the message embedding. This approach is applying the concept of symmetric-key encryption protocol onto steganography. Furthermore, 1bit of symmetric-key is generated by the self-reference of each pixel. Proposed method provide more 25% embedding rate against existing XOR operation-based methods and show the effect of the reversal rate of LSB about 2% improvement.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1759-1769
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• 1997

The Error BackPropagation (EBP) algorithm for multi-layered neural networks is widely used in various areas such as associative memory, speech recognition, pattern recognition and robotics, etc. Nevertheless, many researchers have continuously published papers about improvements over the original EBP algorithm. The main reason for this research activity is that EBP is exceeding slow when the number of neurons and the size of training set is large. In this study, we developed new learning speed acceleration methods using variable learning rate, variable momentum rate and variable slope for the sigmoid function. During the learning process, these parameters should be adjusted continuously according to the total error of network, and it has been shown that these methods significantly reduced learning time over the original EBP. In order to show the efficiency of the proposed methods, first we have used binary data which are made by random number generator and showed the vast improvements in terms of epoch. Also, we have applied our methods to the binary-valued Monk's data, 4, 5, 6, 7-bit parity checker and real-valued Iris data which are famous benchmark training sets for machine learning.